IP design and verification services.
Lumees Lab designs and verifies digital IP for FPGA and ASIC projects: new RTL blocks in SystemVerilog and VHDL, testbenches and verification environments for existing designs, and FPGA prototyping.
Languages and methods
- SystemVerilog
- VHDL-2008
- UVM
- cocotb
- OSVVM
- UVVM
- SVA
- SystemRDL
- IP-XACT
- AXI4
Design and verification, separately or together.
IP development
Digital IP blocks designed to your specification.
Includes
- Specification and micro-architecture
- RTL design in SystemVerilog and VHDL
- AXI4, AXI4-Lite and AXI4-Stream interfaces and register maps
- C and C++ reference models and drivers
- FPGA implementation and prototyping
- Documentation and integration support
Testbench and verification development
Verification for your RTL or for third-party IP.
Includes
- Verification planning
- UVM, cocotb, OSVVM and UVVM environments
- Constrained-random stimulus, scoreboards and functional coverage
- Assertions and formal verification
- Conformance testing against standards
- Regression and coverage closure
Areas we work in.
Cryptography
AES-GCM, AES-XTS, SHA-3, random bit generators and true random number generators.
Post-quantum cryptography
ML-KEM key encapsulation and ML-DSA digital signatures.
Data compression
LZ4 and Snappy compression and decompression engines.
On-chip interfaces
AXI4, AXI4-Lite and AXI4-Stream, with register maps in SystemRDL and IP-XACT.
Ways to work with us.
Turnkey IP development
A complete block, designed and verified to your specification.
Verification services
Testbenches and verification for your RTL or third-party IP.
Team extension
Our engineers working in your team and your flow.
Verification review
An assessment of an existing testbench, plan and coverage.
Tell us about your project.
Email us with what you need and an engineer will come back to you.
Email us about a project
hello@lumeeslab.comHelpful to include
- What you need: a new block, verification for existing RTL, or a review
- The specification or standard, and the size of the design
- Your languages, verification methodology and tools
- The target, FPGA or ASIC, and your timeline