The analog blocks your digital design drives, in the same run.
Lumina Spice is an analog circuit simulator. It reads SPICE netlists in the dialect open PDKs and ngspice use, runs Verilog-A models directly, and simulates the analog blocks of a SystemVerilog design in one time line with Lumina Sim. It checks a netlist is sound before it simulates, and its results are reproducible on any machine.
Commands from the Lumina Spice guide
- Verilog-A
- compiled from source
- SKY130 · GF180 · SG13G2
- open PDK decks, unchanged
- Reproducible
- same numbers on any machine
- AMS
- one time line with Lumina Sim
What Lumina Spice simulates
Every standard analysis
Operating point, DC, AC, transient, noise, transfer function, sensitivity, poles and zeros, Fourier, S-parameters and loop stability.
RF and periodic
Periodic steady state by shooting, harmonic balance, periodic AC, transfer and noise, and transient noise.
Corners and Monte Carlo
.step, .alter, corners, temperature lists and Monte Carlo of the PDK's statistics. Run k is the same circuit however many runs are made.
Devices and Verilog-A
SPICE3 elements, BSIM3, BSIM4, Gummel-Poon and VBIC, and Verilog-A compact models such as PSP, BSIM-CMG and HICUM, compiled by the built-in compiler or loaded as OSDI libraries.
Layout parasitics
SPEF and DSPF back-annotation with RC reduction.
Reliability
Safe operating area, electromigration and IR drop checks, and BTI and HCI aging.
Large circuits
A partitioned, event-driven FastSPICE transient for circuits too large to solve as one matrix.
Your flow, unchanged
ngspice .control scripts and batch flags, so xschem testbenches run as they are, plus KLayout, a Python module and encrypted IEEE 1735 models.
Mixed-signal with Lumina Sim
Analog blocks join the digital design through connect modules at their boundaries, as in Verilog-AMS.
- SPICE subcircuit
--spice file.sp: every .subckt becomes a module of the same name, its parameters module parameters
- Verilog-A module
--ams-va file.va (or a compiled OSDI library): ports keep their directions
- Your own stub
An empty SystemVerilog module marked as analog, with logic, real or real-nettype ports
Frequently asked
Does Lumina Spice run ngspice netlists?
Yes. It reads the dialect open PDKs and ngspice use, including .control scripts. Where ngspice's mathematics or physics are wrong, Lumina Spice computes the correct answer and documents every difference.
Which PDKs does it support?
The open PDKs SKY130, GF180MCU and IHP SG13G2 run without changes.
Can I simulate SystemVerilog and SPICE together?
Yes. SPICE subcircuits and Verilog-A modules are instantiated as modules in the SystemVerilog design and simulated in one process and one time line with Lumina Sim.
Are results reproducible?
The same netlist gives the same numbers regardless of thread count or machine.
Run your own design on Lumina first.
We are working with a small group of design teams before release. You run your real designs; we fix what you find, and your cases become part of the tests every build must pass.