Lumina Sim · Simulation

4-state simulation for SystemVerilog, Verilog and VHDL, in one run.

Lumina Sim compiles, elaborates and runs your design and testbench in one command, with the file lists and options other simulators take. Class-based UVM testbenches, VHDL with its nine logic values, gate-level netlists with SDF timing and analog blocks all run in the same simulation.

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# a VHDL testbench on OSVVM, with SystemVerilog RTL

$ lumsim --vhdl-work osvvm osvvm/*.vhd \

--vhdl-work work tb/my_tb.vhd rtl/*.vhd \

rtl/core.sv --top my_tb

# a UVM test from the Accellera library

$ lumsim +incdir+$UVM_HOME/src $UVM_HOME/src/uvm_pkg.sv \

+incdir+tb tb/top.sv --top top +UVM_TESTNAME=smoke_test

# run the boot once, start every test from there

$ lumsim -f tb.f --top tb --checkpoint-at 1000000 --checkpoint-socket /tmp/ck &

$ lumsim --restore /tmp/ck +TEST=a --seed 1 --waves a.fst

Commands from the Lumina Sim guide

IEEE 1800-2023: SystemVerilog, design and testbench
VHDL-2008: with std_logic's nine values
UVM 1.2 · 1800.2 · 2.0: from the Accellera sources
Native code: built in the background

Capabilities

What Lumina Sim runs

Four-state, as the standard says

Every SystemVerilog bit is 0, 1, X or Z. An unreset register or a bus with two drivers shows as X, not a guessed value, so reset and contention bugs show up in simulation, not in the lab.

VHDL with nine values

std_ulogic keeps U X 0 1 Z W L H and -, resolution follows the standard's table, and VHDL's run-time checks on indices, ranges and lengths are made. --vhdl-one-bit trades the nine values for speed.

Mixed language, no wrappers

A VHDL component instantiates a SystemVerilog module by its name, and a SystemVerilog design instantiates a VHDL entity. Integer, std_ulogic and std_logic_vector ports cross between them.

The testbench you already have

UVM 1.2, IEEE 1800.2-2020 and 2.0, OSVVM, UVVM, cocotb through VPI, C and C++ models through DPI-C, and a Python module to drive a run.

Gate level with timing

Specify blocks, path delays, timing checks with notifiers and negative limits, user-defined and switch-level primitives, and SDF back-annotation per instance.

Fast from the first moment

A run starts at once in compiled code and moves to native machine code built in the background. Checkpoints let every test start after a long reset or boot.

Analog in the same time line

SPICE subcircuits and Verilog-A modules run in Lumina Spice, joined to the digital nets by connect modules as in Verilog-AMS.

Planned

SystemC, VHDL-2019 and PSL

SystemC models through signal ports and TLM-2.0 sockets on the same kernel, the VHDL-2019 additions, and PSL assertions.

Reference

Languages and standards

IEEE 1800-2023 SystemVerilogAvailable
Classes, interfaces, clocking blocks, programs, constraints, covergroups, concurrent assertions
VerilogAvailable
Designs and netlists, user-defined primitives, switch-level primitives with strengths
IEEE 1076-2008 VHDLAvailable
Configurations, package generics, protected types, external names, force and release, std.textio
IEEE 1800.2 UVMAvailable
Accellera UVM 1.2, 1800.2-2020 and 2.0, with register models
OSVVM · UVVMAvailable
OSVVM whole; UVVM's utility library, VVC framework and verification IP
IEEE 1497 SDFAvailable
IOPATH, INTERCONNECT, PORT and NETDELAY delays and timing checks
IEEE 1735Available
Encrypted IP, kept hidden in messages, waves, VPI, the debugger and coverage
IEEE 1666 SystemCPlanned
Signal ports and TLM-2.0 sockets, one scheduler
IEEE 1076-2019 VHDLPlanned
The 2019 additions

Standard	What runs	Status
IEEE 1800-2023 SystemVerilog	Classes, interfaces, clocking blocks, programs, constraints, covergroups, concurrent assertions	Available
Verilog	Designs and netlists, user-defined primitives, switch-level primitives with strengths	Available
IEEE 1076-2008 VHDL	Configurations, package generics, protected types, external names, force and release, std.textio	Available
IEEE 1800.2 UVM	Accellera UVM 1.2, 1800.2-2020 and 2.0, with register models	Available
OSVVM · UVVM	OSVVM whole; UVVM's utility library, VVC framework and verification IP	Available
IEEE 1497 SDF	IOPATH, INTERCONNECT, PORT and NETDELAY delays and timing checks	Available
IEEE 1735	Encrypted IP, kept hidden in messages, waves, VPI, the debugger and coverage	Available
IEEE 1666 SystemC	Signal ports and TLM-2.0 sockets, one scheduler	Planned
IEEE 1076-2019 VHDL	The 2019 additions	Planned

Questions

Frequently asked

What does 4-state simulation mean?

Every bit can be 0, 1, X (unknown) or Z (high impedance). An uninitialised register or a net with two drivers shows as X instead of a guessed 0 or 1, so reset and contention bugs appear in simulation rather than in silicon. VHDL designs keep std_logic's nine values by default.

Can I simulate VHDL and SystemVerilog together?

Yes. A VHDL component with no VHDL entity of its name is an instance of the SystemVerilog module of that name, and SystemVerilog instantiates a VHDL entity by its name in lower case. Integer, std_ulogic and std_logic_vector ports cross between the languages.

Will my existing UVM testbench run?

UVM 1.2, 1800.2-2020 and 2.0 run from the Accellera sources, with or without UVM's C library. Testbenches that rely on what another simulator lets pass can use --compat all, which relaxes the rules they most often break.

Does Lumina Sim support cocotb?

Yes, through VPI. It works with cocotb's Python runner and with its makefile flow.

Which platforms does it run on?

Linux x86-64 today. Windows x86-64 and macOS on Apple silicon are planned.

Run your own design on Lumina first.

We are working with a small group of design teams before release. You run your real designs; we fix what you find, and your cases become part of the tests every build must pass.

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