The whole chip front end. One tool. Built for engineers and their AI agents.
Write it, lint it, simulate it, prove it, cover it, debug it. Lumina takes your RTL from first line to sign-off-ready in one system: SystemVerilog, VHDL, SystemC and analog in one simulation, lint and CDC as you type, formal proofs on the same design, and every result in a form a person or an AI agent can read and act on.
- ✕No glue scripts
- ✕No five-vendor licence spreadsheet
- ✕No second compile
Everything between your spec and your netlist.
Most teams build their front end out of tools that were never meant to meet: one for lint, another for CDC, a simulator per language, a formal tool with its own compile, coverage in yet another format. Lumina is one system with one model of your design.
Lumina Sim
SystemVerilog, Verilog, VHDL, SystemC and analog in one simulation. UVM, OSVVM, UVVM, cocotb.
Lumina Lint
Hundreds of rules, FPGA and ASIC rule packs, results in your editor as you type.
Lumina CDC
Clock and reset domain crossings, checked against your SDC and XDC.
Lumina Formal
Assertions proved or broken with a counterexample; multicycle paths proved.
Coverage
Functional, code, expression, condition and FSM, merged and ranked across runs.
Debug
Waves, source and drivers in one view, in the editor you already use.
Lumina Reg
Registers from SystemRDL or IP-XACT to RTL, C headers, UVM models and docs.
Lumina Spice
The analog blocks your digital design drives, in the same run.
Lumina Protect
Your IP encrypted for any IEEE 1735 tool your customer runs.
One design model. They are not separate products to buy and wire together: one install, one licence, one compile feeds them all.
Your agent can run the regression now.
AI coding agents are only as good as the tools they can call and the results they can read. Lumina was built to be driven by machines as well as people.
- An MCP server.Planned Lumina speaks the Model Context Protocol. Point Claude, or any MCP-capable agent, at it, and the agent can compile a design, run lint and CDC, launch a simulation, read the failing assertion, query a waveform at a time and signal, check coverage holes and ask the formal engine for a counterexample.
- Results an agent can parse.Coverage and test data planned Findings as JSON and SARIF. The design's clocks, crossings, state machines and netlist as JSON. Coverage and test results as structured data, not log lines to scrape.
- Answers with evidence. A finding carries the file, the line, the rule and why. A failure carries the time, the signal and the value. An agent can fix the cause, not guess at the symptom.
- A loop that closes. Agent writes RTL, Lumina checks it, agent reads the result and fixes it, Lumina checks again. Minutes, not review cycles.
- Python, C and the editor protocols. A Python module for every engine, a C API, the Language Server Protocol for editors, the Debug Adapter Protocol for stepping through a simulation. Use them from scripts, notebooks, CI or your own agents.
You stay in charge: agents get the same tools and the same evidence your engineers see, and every run is recorded.
- 1lumina.compile(top="uart_bridge")elaborated
- 2lumina.cdc(sdc="constraints/top.sdc")1 unsafe crossing
- 3rtl/uart_rx.sv:88 rx_valid clk_uart → clk_sys no synchronizer
- 4rtl/uart_rx.sv add 2-flop synchronizer on rx_valid
- 5lumina.cdc()0 unsafe crossings
- 6lumina.sim(test="burst_test")UVM_ERROR 0
{
"rule": "CDC-UNSYNC",
"file": "rtl/uart_rx.sv",
"line": 88,
"signal": "rx_valid",
"from": "clk_uart",
"to": "clk_sys",
"why": "single-bit crossing with no synchronizer"
}Every language your chip speaks, in one simulation.
A VHDL entity can instantiate a SystemVerilog module, which can instantiate a SystemC model, which talks to an analog block. Each language keeps its own rules: VHDL's nine logic values and delta cycles, SystemVerilog's scheduling regions, SystemC's processes and TLM sockets. No wrappers. No bridges to maintain.
SystemVerilog and Verilog
The full design and testbench language: classes, interfaces, clocking blocks, constraints, covergroups and concurrent assertions.
VHDL
VHDL-2008 and 2019, with std_logic's nine values, configurations, external names, force and release, and the run-time checks VHDL defines.
SystemC
SystemC models in the same run as your RTL, through signal ports and TLM-2.0 sockets, scheduled by one kernel.
Analog and mixed-signal
Verilog-A modules and SPICE netlists solved by Lumina Spice, with the digital side at every time step it needs.
Bring the testbench you already have. Keep all of it.
Lumina runs the open verification libraries as they are published. Your UVM environment, your OSVVM components, your cocotb tests: they run as they are.
- UVM
- 1.2 and IEEE 1800.2, including register models.
- OSVVM and UVVM
- for VHDL teams, with their scoreboards, coverage and verification components.
- cocotb and Python
- through VPI, and a Python module to drive a simulation directly.
- DPI-C and VPI
- for C models, reference algorithms and tools of your own.
- Assertions
- in SVA and PSL, with their coverage. PSL planned
- Coverage
- functional, line, toggle, expression, condition and state machine, merged across runs and ranked by which tests add the most. expression · condition · FSM · ranking planned
Illustrative output
The bugs that cost the most are the ones you find last.
Lint and CDC run on the same design model the simulator uses, so they are cheap to run on every save. A clock-domain crossing the lint flags is one the formal engine can prove safe or show failing. A constraint file is checked against the design it constrains, and written from it when you don't have one yet.
Lint
with rule packs for FPGA, ASIC and safety-minded design.
CDC and RDC
synchronizers recognised, unsafe crossings explained.
SDC and XDC
clocks, false paths and multicycle paths checked against the RTL; multicycle paths proved by the formal engine.
Formal
assertions proved for all inputs, or broken with a short trace.
Find the cause, not just the failure.
Interactive debug
- Waveforms in your editor: the waves, the source with the values at the cursor time, and the hierarchy, in one window.Planned
- Drivers and loads: from a wrong value, step back to the process and the line that wrote it.Planned
- Breakpoints and stepping: in SystemVerilog and VHDL code, from the terminal or the editor.
- Checkpoints: save a long run at any time and start the next experiment from there.
- Findings beside the waves: lint and CDC results on the signals they concern.
Gate-level and sign-off
- Gate-level simulation: with SDF timing and timing checks.
- FPGA vendor libraries: compiled and tested, so a vendor IP simulation works the first time.Planned
- Encrypted IP: under IEEE 1735, read and written.
- Power intent: (IEEE 1801 UPF) in simulation.Planned
Built for the way teams ship chips.
- AvailableLinuxx86-64
- PlannedWindowsx86-64
- PlannedmacOSApple silicon
Floating licences
Seats shared from a licence server across the team, with features you turn on as you need them.
Made for CI
Exit codes, reports and coverage databases that a regression farm reads without scraping logs.
Traceable results
Every test linked to the requirement it checks, and every run kept, so a release is decided by evidence, not by memory.
Tested in the open
Checked continuously against the published verification libraries and open designs, with every result recorded.
Run your own design on it first.
We are working with a small group of design teams before release. You run your real designs; we fix what you find, and your cases become part of the tests every build must pass.
Chip and FPGA startups
Teams on open simulators who need lint, CDC and formal without a six-figure budget.
Design services
Firms working across VHDL and SystemVerilog for many clients.
Research groups
Labs that want one tool for teaching, research and tape-out.
Test partner program
Program detailsDesign partner
Co-develop Lumina on your production designs.
- The full Lumina system: every engine, every build, as it lands
- A direct engineering channel to the Lumina developers
- Priority triage: what blocks your design is fixed first
- Your cases added to the tests every build must pass
Evaluation partner
Test release candidates on your own designs.
- Release-candidate builds of Lumina
- Issue tracker access with engineering follow-up
- Your reported cases folded into the regression suite
- Release notes and early documentation
The technology underneath, and the IP ecosystem around it.
The same evidence-first method runs through everything Lumees Lab builds: building blocks verified like silicon IP, process kits where every number is traceable, and IP and VIP from our partners, tested on Lumina.