Tested building blocks for the larger design.
Lumina Blocks are starting points for larger systems: SystemVerilog components written and verified to the standard of silicon IP, available alongside Lumina. Every block is checked against the published conformance vectors for its standard, built from one source on AMD, Altera and Efinix devices, and delivered with a C++ model, a C driver, register descriptions and an integration guide.
Conformance: CAVP · ACVP · IEEE 1619 Annex B · SP 800-22 · LZ4 and Snappy format specs
LM-AES-GCM
v0.2.0AES-GCM Crypto Engine
One block per clock · Fully unrolled cipher · Tag verification in hardware · Portable to any FPGA
LM-AES-XTS
v0.1.0AES-XTS Storage Encrypt/Decrypt Engine
One block per clock · Register-free sector pipelining · Integrated key expansion · Portable to any FPGA
LM-DRBG
v0.1.0Deterministic Random Bit Generator
SP 800-90A CTR_DRBG · AES-256 with derivation function · Prediction resistance · Health tests on every path
LM-SHA3
v1.0.0SHA-3 Hash Crypto Engine
High throughput · Fixed-latency permutation · Register-based configuration · Portable to any FPGA
LM-TRNG
v0.1.0True Random Number Generator
Ring-oscillator entropy source · SP 800-90B health tests · AIS-31 total-failure detection · Portable to any FPGA
LM-PQC-D
v0.1.0ML-DSA Digital Signature Engine
Timing and SPA resistant by construction · Hedged or deterministic signing · All three parameter sets · Portable to any FPGA
LM-PQC-K
v0.3.0ML-KEM Key Encapsulation Engine
Timing and SPA resistant by construction · Pre-operational self-test · All three parameter sets · Portable to any FPGA
LM-LZS-D
v0.1.0LZ4/Snappy Data Decompressor
Up to 8 bytes per clock · Automatic format detection · Errors that name the failing check · Portable to any FPGA
LM-LZS-E
v0.1.0LZ4/Snappy Data Compressor
Standards-compliant framing emitted by the core · Configurable search window · Stored-block fallback · Portable to any FPGA
Components for the system you are building.
Verified like silicon IP
Conformance vectors, formal checks and measured FPGA results: the same evidence production IP is held to.
Made to be built on
Plain AXI4 interfaces and register descriptions in SystemRDL and IP-XACT, so a block becomes part of your design, not a sealed box.
Ready for Lumina
Every block is simulated, linted and checked on Lumina, so it drops into a Lumina flow and its tests run as they are.
Silicon-ready IP from partners
Lumina Blocks are starting points and come without IP guarantees. Finished, guaranteed IP and VIP come from Lumina IP partners.
IP partnersThe blocks a larger system needs next.
Lumina Blocks grow toward complete systems. These families are in development.
- Planned
RISC-V cores
RISC-V processor cores to build a system around.
- Planned
GPU
Graphics and parallel compute engines.
- Planned
AXI infrastructure
Crossbars, bridges and width and clock converters for AXI4 systems.
- Planned
Interfaces
Peripheral and chip-to-chip interfaces.
- Planned
Interconnect
On-chip interconnect and networks-on-chip.
Available on request, alongside Lumina.
Tell us what you are building and which blocks you need. An engineer will come back to you with the datasheets and the terms.
Request Lumina Blocks
hello@lumeeslab.comHelpful to include
- The blocks you are interested in
- The system you are building and its target: FPGA or ASIC
- Whether you use Lumina already or would like to