What we are building next.
Two longer projects in the design stage: an open GPU instruction set anyone can implement, and a high-level synthesis tool that turns C++ into RTL and verifies it on Lumina. Neither is a product yet. We publish the plans early because both need partners to get right.
An open GPU instruction set
A royalty-free GPU instruction set that anyone can implement, from one small core to mobile, desktop and server profiles. The aim is to do for GPUs what RISC-V did for CPUs.
High-level synthesis, verified
C++ and SystemC to Verilog, SystemVerilog and VHDL, for any FPGA and any standard-cell library, with every generated design simulated against its C++ testbench and linted in Lumina.
Plans, not products. Scope and details will change as the work is proved.
Proof before claims.
Proved in stages
Each project moves in phases, and a phase ends only when its tests and benchmark designs pass. Nothing goes on this page as done until it runs.
Clean room
Built from standards, published papers and open tools. Commercial tools' manuals, outputs and examples are never used.
Open where it counts
Specifications and the parts that stop lock-in are planned to be open, so others can build on them and check our work.
An open GPU instruction set
Today every GPU has its own closed instruction set, and the compilers and drivers for it belong to its vendor. We are designing an open one: a small core that is frozen once and never broken, extensions for graphics, ray tracing and AI, and three profiles built from the same encoding. One compiler and driver stack can then serve every implementation.
- Royalty-free
- Mobile · Desktop · Server
- Graphics and compute
- FP8, FP6, FP4, MX formats
Small core, modular extensions
Integer and FP32 arithmetic, branches, memory, atomics, barriers and wave operations in the core. Graphics, ray tracing, tensor operations, micro number formats, asynchronous copies, multi-GPU and privileged operations come as extensions.
Three profiles, one encoding
Mobile for tile-based, low-power graphics; desktop for rasterisation, ray tracing and compute; server for AI training and inference at scale. A server part may drop the graphics units, but the instruction encoding stays shared.
AI number formats from the start
FP16, BF16, FP8, FP6 and FP4, block-scaled (MX) formats and 2:4 sparsity are designed in, not added later.
A stable virtual ISA
Compilers target a versioned virtual instruction set that SPIR-V and LLVM/MLIR can produce directly, so code keeps running across hardware generations. The physical instruction set is published too, so independent hardware is possible.
Independent of the microarchitecture
Wave width, register file size and cache hierarchy are parameters software queries, not fixed in the ISA. Dependency hints in each instruction let the compiler do the scheduling, so hardware can stay simple.
Secure from the start
Memory isolation, virtualisation, multi-tenant partitioning and confidential computing are part of the server profile, not an afterthought.
Open by design
- Specification
- Planned under CC BY 4.0: free to implement, no royalties, no permission needed.
- Reference software and RTL
- Planned under Apache 2.0.
- Patents
- A written pledge not to assert our patents against implementations.
- Governance
- Moved to an independent foundation before version 1.0 is frozen, with public drafts and comment periods.
- Conformance
- A compatibility mark only for designs that pass the conformance test suite, ours included.
How it will be proved
- An executable reference model of the specification; where the text is unclear, the model decides.
- Functional and cycle-approximate simulators, so compilers and drivers can be built before any silicon exists.
- A conformance test suite covering every instruction, every extension and memory-model litmus tests.
- A small open RTL core that fits an FPGA, to show the specification can really be built.
- Software goals: an LLVM back end and MLIR dialect, a Vulkan driver in Mesa, OpenCL and SYCL, then Triton and PyTorch support.
Looking for
Universities and research groups, compiler and driver engineers, and chip companies that want a GPU instruction set no single vendor controls. Early reviewers of the draft are welcome.
High-level synthesis, verified
High-level synthesis lets an algorithm written in C++ become hardware. Today the tools either target one FPGA vendor's devices, or are sold to large companies with the simulator, lint and equivalence checker as further products. We are planning one tool for any FPGA and any ASIC library, with verification built in: the RTL it writes is checked on Lumina against the same C++ it came from.
- C++ and SystemC in
- Verilog, SystemVerilog, VHDL out
- Any FPGA, any ASIC library
- Verified on Lumina
Verification included
C/RTL co-simulation in Lumina with the C++ testbench reused on the RTL, waves shown beside the C++ source, lint of every output; a formal proof that the RTL equals the C++ is planned.
One source, any target
FPGAs from several vendors and ASICs through any Liberty cell library, starting with open PDKs such as SkyWater 130 and IHP 130. Code moves between devices without a rewrite.
Open input types
Bit-accurate integer and fixed-point types from the open Algorithmic C library, and SystemC types, so designs are not locked to our tool.
Interfaces generated
AXI4, AXI4-Lite, AXI4-Stream and Avalon; valid/ready handshakes, FIFOs and memory ports; a control register block with a C header for software.
Readable output
Generated RTL keeps names and comments tied to the C++ lines, so reviewers and lint can follow where each part came from.
Reports you can act on
Latency, throughput, resources and estimated timing per design, and a schedule view that maps clock cycles back to source lines.
The flow
- Write and test
- Synthesizable C++ or SystemC, tested as ordinary software with a debugger.
- Direct
- Pipeline, unroll, partition arrays, dataflow between functions, choose interfaces and the clock.
- Synthesize
- Schedule and bind for a clock target on a chosen device or cell library.
- Verify
- Co-simulate against the C++ testbench in Lumina and lint the result.
- Export
- RTL, an IP-XACT package, timing constraints and synthesis scripts, and a C driver.
How it will be proved
- Every generated design in every phase co-simulated in Lumina against its C++ testbench, and linted.
- Open HLS benchmark suites synthesized, matching their C++ and meeting timing on an FPGA family and an open PDK.
- A first full flow with open tools: a streaming image filter from C++ to a bitstream running on a real board.
- Bugs planted by hand in generated RTL (wrong rounding, an off-by-one loop bound, a dropped stream element) caught every time.
- Three customer-style designs (an image filter, a FIR/FFT chain, a small neural-network layer) taken to verified RTL by a new user with the guide alone.
Looking for
Design partners with algorithms in C++ (imaging, signal processing, small neural-network layers) who would try early builds and tell us what is missing.
Want to help shape these?
If you would review a draft, try an early build or work with us on either project, write to us.
Research
hello@lumeeslab.comHelpful to include
- Which project interests you
- Your team or research group
- How you would like to take part