Learn chip design on the tool you will use.
Online courses that take you from logic fundamentals to sign-off-ready RTL. Every lab runs on Lumina, every project ends in real tool output, and the work is graded from Lumina's own results, the way a team signs off a block.
- Online, self-paced
- Hands-on labs on Lumina
- Graded from tool output
- SystemVerilog and VHDL
- English and Türkçe
Learn by building, check by running.
Labs on Lumina
Every module has a lab you run on Lumina: simulation, lint, CDC, formal and coverage on one design model, in a Linux lab image with Lumina installed.
Graded from results
Submissions are checked automatically from Lumina's JSON and SARIF output, coverage and exit codes: correctness, clean lint and CDC, verification evidence and documentation.
Gates, not quizzes
Each level ends in a gate on real work: a block that meets timing, a coverage target closed, a sign-off package. Engineers with experience can take a gate directly and skip the level.
One design, all the way
The block you write in Level 2 is the one you verify in Level 3 and sign off in Level 4, so every step builds on the last, as it does on a real project.
Four core levels, seven tracks, one capstone.
Take the core levels in order, then specialise in one or two tracks and finish with a team capstone.
Core levels
Foundations of digital hardware
Logic, sequential circuits, state machines, timing and arithmetic: think in circuits before you write serious RTL.
6 weeks · Beginner · 6 modules
RTL design in SystemVerilog and VHDL
Synthesizable SystemVerilog and VHDL-2008 side by side, datapaths, FIFOs, AXI and FPGA implementation, with lint on every save.
8 weeks · Intermediate · 8 modules
Verification: UVM, cocotb, assertions and formal
Verify one design four ways, with UVM, cocotb, OSVVM and formal, then close coverage and debug to the root cause.
10 weeks · Intermediate · 10 modules
Static checks and sign-off
Lint, clock and reset domain crossings, constraints, registers as code and IP delivery: the checks that catch the most expensive bugs.
5 weeks · Advanced · 6 modules
Specialisation tracks
Hardware security and cryptography
AES-GCM and XTS, SHA-3, random number generation, constant-time design and side-channel basics, on the Lumina Blocks crypto line.
6–8 weeks · Advanced · 7 topics
Post-quantum cryptography
Lattice maths, NTT hardware, ML-KEM and ML-DSA, Keccak reuse, masking and ACVP vector testing.
6–8 weeks · Advanced · 7 topics
Data compression hardware
The LZ77 family, hash-chain match finders, LZ4 and Snappy formats and decoders that output several bytes per clock.
6–8 weeks · Advanced · 5 topics
SoC and processor design
The RISC-V ISA, a five-stage pipeline, caches, AXI crossbars and converters, networks-on-chip, interrupts and boot.
6–8 weeks · Advanced · 6 topics
ASIC physical design
Synthesis, floorplan, placement, clock trees, routing and timing across corners, on Lumees Lab's predictive PDKs.
6–8 weeks · Advanced · 7 topics
Mixed-signal and analog interfaces
Verilog-A, SPICE, real-number modelling, ADC, DAC and PLL behavioural models, and digital-analog co-simulation.
6–8 weeks · Advanced · 5 topics
Safety-critical and AI-assisted design
DO-254 and ISO 26262 processes, fault injection and traceability, and driving Lumina from an AI agent with a human signing off.
6–8 weeks · Advanced · 6 topics
Total: About 29 weeks for the four core levels, plus 6–8 weeks per track and 6 weeks of capstone.
Three paths, three certificates.
A path is a sequence of courses that ends in a certificate earned on real work. Certificates are planned for when the courses open.
Lumina Certified RTL Designer
For FPGA and ASIC RTL engineers: synthesizable SystemVerilog and VHDL, micro-architecture, AXI, FPGA implementation and sign-off checks. This path goes from Level 2 straight to Level 4.
Lumina Certified Verification Engineer
For design verification engineers: UVM, cocotb, OSVVM and UVVM, assertions, formal and coverage closure.
Lumina Certified Specialist
For domain experts: the four core levels, one specialisation track and a team capstone, for example in cryptography or post-quantum IP.
Start where your experience is.
| You are | Start at | Typical path |
|---|---|---|
| A university student in EE or CE | Level 1 | All four levels, then a track and a capstone |
| An FPGA engineer moving to ASIC | Level 2 | Levels 2–4 and Track E, physical design |
| A software engineer moving to hardware | Level 1 | Levels 1–3 and Track G, with Python (cocotb) verification |
| An experienced DV engineer | Level 3 gate | Levels 3–4 fast, then Track A or B |
| A team adopting Lumina | Level 4 gate | The Lumina-specific parts of each level |
Online first, also for universities and teams.
Online, self-paced
Reading and hands-on labs, a Linux lab image (container or virtual machine) with Lumina installed, and automatic grading.
University courses
A two-semester elective on Lumina, with lecture material, lab kits and automatic graders for the lecturer.
Team training
Levels 2–4 condensed for engineering teams moving to Lumina from other tools.
Be the first to know when the courses open.
Write to us to hear when the first courses open, or to talk about a university course or training for your team.
Training
hello@lumeeslab.comHelpful to include
- Who you are, and whether you're learning yourself, teaching, or training a team
- The courses or tracks you're most interested in
- English or Turkish