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Track F
Coming soonMixed-signal and analog interfaces
Most chips have analog at their edges. Model it at the right level, from SPICE to behavioural Verilog-A, and simulate it with the digital design in the same run.
- Duration
- 6–8 weeks
- Level
- Advanced
- Before you start
- The four core levels, or their gates.
What you'll learn
- Write Verilog-A and SPICE models
- Model ADCs, DACs and PLLs behaviourally and with real numbers
- Run digital and analog together in one simulation
Syllabus
5 topics
- 01
Verilog-A
- 02
SPICE
- 03
Real-number modelling
- 04
Behavioural models of ADCs, DACs and PLLs
- 05
Digital-analog co-simulation
Coming soon
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