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Track E
Coming soonASIC physical design
Take RTL to layout on a realistic process. The track runs on Lumees Lab's predictive PDKs, which have the transistor models, standard cells, timing libraries and wiring data a real kit has, without a foundry NDA.
- Duration
- 6–8 weeks
- Level
- Advanced
- Before you start
- The four core levels, or their gates.
What you'll learn
- Synthesise, floorplan, place, build clock trees and route a block
- Close timing across process, voltage and temperature corners
- Analyse IR drop and wire-dominated paths
- Account for aging and variability in sign-off
Syllabus
7 topics
- 01
Synthesis
- 02
Floorplan and placement
- 03
Clock tree synthesis
- 04
Routing
- 05
Static timing across PVT corners
- 06
IR drop and wire-dominated paths
- 07
Aging and variability
Coming soon
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