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Level 4
Coming soon

Static checks and sign-off

Level 4 teaches the checks that catch the most expensive bugs before simulation, the way Lumina catches them as you type. It closes with a full sign-off review of your own block.

Duration
5 weeks
Level
Advanced
Before you start
Level 3, or its gate. On the RTL Designer path, Level 2 is enough.
What you'll learn
  • Run lint as a gate, with every waiver justified
  • Design and justify every clock and reset domain crossing
  • Write constraints that match the design
  • Keep one source of truth for registers
  • Deliver encrypted IP a customer can run
Syllabus

6 modules

  1. 4.1

    Lint in depth

    Safety rule pack · Planned

    Topics

    Rule categories, FPGA, ASIC and safety rule packs, waivers and their justification

    Lumina lab

    Triage 200 findings on an inherited code base and waive with reasons

    You can

    Run lint as a gate, not a chore

  2. 4.2

    Clock domain crossing

    Topics

    Metastability and MTBF, two-flop synchronisers, pulse synchronisers, handshakes, asynchronous FIFOs, reconvergence

    Lumina lab

    Fix the UART bridge's unsafe crossing and prove it safe with Lumina Formal

    You can

    Design and justify every crossing

  3. 4.3

    Reset domain crossing

    Topics

    Asynchronous assert and synchronous deassert, reset trees, RDC hazards

    Lumina lab

    Find and fix an RDC bug in a design with several resets

    You can

    Plan resets as carefully as clocks

  4. 4.4

    Constraints (SDC and XDC)

    Topics

    Clocks, generated clocks, false and multicycle paths, I/O delays

    Lumina lab

    Write the SDC from the RTL and prove the multicycle paths with Lumina Formal

    You can

    Write constraints that match the design

  5. 4.5

    Registers as code

    Topics

    SystemRDL and IP-XACT, generating RTL, C headers, UVM register models and documentation

    Lumina lab

    Regenerate the Level 2 block's registers with Lumina Reg

    You can

    Keep one source of truth for registers

  6. 4.6

    Gate-level simulation and IP delivery

    Topics

    Gate-level simulation with SDF, timing checks, IEEE 1735 encryption, release packaging

    Lumina lab

    Encrypt a block with Lumina Protect and simulate the encrypted netlist

    You can

    Deliver IP a customer can run

Gate to the tracks

A sign-off package for one block: lint and CDC reports clean or waived, SDC, a coverage report, register documentation and an encrypted release.

Coming soon

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