Verification: UVM, cocotb, assertions and formal
Level 3 is the longest level, because verification is where most of the work on a chip project goes. You verify the same design four ways, so you can judge which method fits which problem.
- Duration
- 10 weeks
- Level
- Intermediate
- Before you start
- Level 2, or its gate.
- Write a verification plan before the testbench
- Build self-checking, constrained-random testbenches and a reusable UVM VIP
- Verify in Python with cocotb, and in VHDL with OSVVM and UVVM
- Write assertions once and use them in simulation and formal
- Know when formal beats simulation
- Argue sign-off with coverage data, and verify against a published standard
10 modules
- 3.1
Verification planning
Topics
From specification to plan, features, requirements traceability, coverage model, sign-off criteria
Lumina lab
Write a verification plan for the AXI block from Level 2
You can
Plan before writing a testbench
- 3.2
SystemVerilog for verification
Topics
Classes, randomisation and constraints, interfaces, clocking blocks, mailboxes, DPI-C
Lumina lab
A constrained-random AXI4-Lite driver with a C reference model
You can
Build a self-checking testbench
- 3.3
UVM (IEEE 1800.2)
Topics
Agents, sequences, scoreboards, the factory, the configuration database, RAL register models
Lumina lab
A full UVM environment, run with lumsim +UVM_TESTNAME and coverage on
You can
Ship a reusable UVM VIP
- 3.4
Python verification with cocotb
Topics
Coroutines, drivers and monitors, reference models in Python, VPI
Lumina lab
Verify the same design again in cocotb and compare effort and run time
You can
Pick Python where it is faster
- 3.5
VHDL methodologies
Topics
OSVVM and UVVM components, scoreboards, coverage
Lumina lab
An OSVVM testbench for the VHDL state machine from 2.2
You can
Serve VHDL-first teams
- 3.6
Assertions
PSL · PlannedTopics
Immediate and concurrent SVA, properties and sequences, assertion coverage; PSL
Lumina lab
Protocol assertions for AXI4-Stream valid/ready
You can
Write checkers once and reuse them in simulation and formal
- 3.7
Formal verification
Topics
Model checking, assumptions and assertions, bounded and full proofs, counterexamples, equivalence
Lumina lab
Prove the asynchronous FIFO never overflows, then break it and read the trace
You can
Know when formal beats simulation
- 3.8
Coverage closure
Expression, condition and FSM coverage, test ranking · PlannedTopics
Functional, line, toggle, expression, condition and FSM coverage; merging and test ranking
Lumina lab
Merge the results of four testbenches, rank the tests and close the holes
You can
Argue sign-off with data
- 3.9
Debug
Topics
Waveforms, driver tracing, breakpoints, checkpoints, a root-cause method
Lumina lab
A seeded-bug hunt: ten bugs, two hours
You can
Find the cause, not the symptom
- 3.10
Conformance testing
Topics
Standards test vectors (NIST CAVP and ACVP, IEEE 1619 Annex B), golden-model comparison
Lumina lab
Run the CAVP SHA-3 vectors against LM-SHA3
You can
Verify to a published standard
Gate to Level 4
All planned functional coverage closed on the Level 2 block, with at least one formally proven property.
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