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Track D
Coming soonSoC and processor design
Put a system together around a processor: build a pipelined RISC-V core, connect it over AXI, and bring it up from reset to running code.
- Duration
- 6–8 weeks
- Level
- Advanced
- Before you start
- The four core levels, or their gates.
What you'll learn
- Implement a five-stage RISC-V pipeline and resolve its hazards
- Add caches and connect a system over AXI crossbars and converters
- Explain network-on-chip basics
- Handle interrupts and boot a system
Syllabus
6 topics
- 01
The RISC-V ISA
- 02
A five-stage pipeline and its hazards
- 03
Caches
- 04
AXI crossbars, width and clock converters
- 05
Network-on-chip basics
- 06
Interrupts and boot
Coming soon
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