RTL design in SystemVerilog and VHDL
Level 2 teaches synthesizable SystemVerilog and VHDL-2008 side by side, because real projects use both and Lumina simulates both in one run. Lint runs on every save from the first module, so clean-code habits form early.
- Duration
- 8 weeks
- Level
- Intermediate
- Before you start
- Level 1, or its gate.
- Write lint-clean, synthesizable SystemVerilog
- Read and write SystemVerilog and VHDL fluently, in one design
- Design flow-controlled pipelines and know when a FIFO needs two clocks
- Write a micro-architecture specification before the RTL
- Integrate a block over AXI4-Lite and AXI4-Stream
- Package a block another team can drop in
8 modules
- 2.1
SystemVerilog for design
Topics
always_ff and always_comb, packages, interfaces, parameters, generate, enums and structs
Lumina lab
Port the Level 1 state machines and drive the lint findings to zero
You can
Write lint-clean, synthesizable SystemVerilog
- 2.2
VHDL-2008 for design
Topics
The nine values of std_logic, records, generics, process sensitivity, the VHDL-2008 additions
Lumina lab
The same state machine in VHDL, instantiated from a SystemVerilog top in one simulation
You can
Read and write both languages fluently
- 2.3
Datapath and control
Topics
Splitting datapath and controller, valid/ready handshakes, back-pressure
Lumina lab
A streaming FIFO with valid/ready, with its corner cases followed in Debug
You can
Design flow-controlled pipelines
- 2.4
Memories and FIFOs
Topics
Inferred RAM and ROM, synchronous and asynchronous FIFOs, Gray-code pointers
Lumina lab
An asynchronous FIFO, reused later in the CDC module
You can
Know when a FIFO needs two clocks
- 2.5
Micro-architecture
Topics
Throughput, latency and area, unrolling, pipelining, resource sharing
Lumina lab
Build an AES round three ways and compare cycles and area
You can
Write a micro-architecture specification before the RTL
- 2.6
The AMBA AXI4 family
Topics
AXI4-Lite for control, AXI4-Stream for data, full AXI4 bursts, the protocol rules
Lumina lab
An AXI4-Lite slave and an AXI4-Stream wrapper around the FIFO from 2.3
You can
Integrate any Lumina Block
- 2.7
FPGA implementation
Topics
Synthesis, XDC and SDC constraints, timing closure, the AMD, Altera and Efinix vendor flows
Lumina lab
Build one design for two FPGA vendor families from one source
You can
Report Fmax and resources the way a Lumina Block datasheet does
- 2.8
Design for reuse
Topics
Parameterisation, IP-XACT packaging, documentation, integration guides
Lumina lab
Package the block from 2.6 as IP-XACT
You can
Ship a block another team can drop in
Gate to Level 3
A lint-clean AXI4-Lite and AXI4-Stream block that meets timing on one FPGA family.
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