Verification IP for every interface on your chip.
Verification IP, assertion IP, memory models and synthesizable transactors for more than 200 protocols, from AMBA and PCI Express to DDR5, MIPI and automotive buses. Built for Lumina, so the VIP, the design and the checks share one model.
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Browse by category
- 16
On-chip interconnect
AMBA, TileLink, OCP and other buses inside a chip.
- 15
PCIe, CXL and chiplets
PCI Express, CXL, UCIe and other high-speed links.
- 10
USB
USB 2.0 to USB4, Power Delivery and Type-C.
- 26
DRAM
DDR, LPDDR, GDDR and HBM devices, modules and DFI.
- 16
Flash, SRAM and other memory
NAND, NOR, SRAM, PSRAM and non-volatile memories.
- 9
Storage
NVMe, UFS, eMMC, SD, SATA and SAS.
- 24
Ethernet and networking
Ethernet from 10 Mb/s to 1.6 Tb/s, TSN, security and fronthaul.
- 22
MIPI
Camera, display, PHY, control and debug interfaces.
- 14
Display and video
DisplayPort, HDMI, HDCP, SDI and camera links.
- 13
Automotive
CAN, LIN, FlexRay, SENT and automotive Ethernet and SerDes.
- 11
Aerospace and defence
ARINC, MIL-STD-1553, SpaceWire and SpaceFibre.
- 28
Serial and peripheral
I2C, SPI, UART, JTAG, SMBus, PMBus and more.
- 4
Audio
I2S, TDM, PDM and S/PDIF.
- 4
Processor and coding
RISC-V cores and interrupt controllers, floating point and line coding.
Five ways to verify an interface.
Verification IP
UVM agents that drive and check a protocol in simulation, in every role the protocol defines.
Assertion IP
SystemVerilog assertions, assumptions and cover properties that prove a design follows the protocol in Lumina Formal, or check it in simulation.
Memory model
Device models that behave like the memory part: commands, modes, refresh and every timing parameter checked.
Synthesizable transactor
Synthesizable models of the protocol for FPGA prototyping and hardware-assisted verification, driven from the same tests as the VIP.
Post-silicon validation IP
Drives and checks the bus on a real board through an FPGA, to validate silicon with the scenarios used before tape-out.
One model for the design and its verification IP.
Native on Lumina
VIP runs in Lumina Sim beside your RTL, and assertion IP proves in Lumina Formal. No separate compile and no wrapper layer.
Results you can read
Each protocol violation names the rule it broke and the transaction that broke it, in a form an engineer or an AI agent can act on.
Coverage that merges
Protocol coverage lands in the same coverage database as your own, so one report shows what has and has not been exercised.
SystemVerilog and UVM
Written in SystemVerilog with UVM, and readable source, so your team can extend sequences and checks.
Browse every protocol.
Search by name or filter by category and product type.
AMBA AXI
On-chip interconnectAXI3 · AXI4 · AXI5
Manager, subordinate and interconnect models for the AXI family, with outstanding and out-of-order transactions, bursts, atomics and AXI5 extensions.
VIPAIPTransactorAMBA AXI-Lite
On-chip interconnectAXI4-Lite · AXI5-Lite
Register-style AXI-Lite traffic for control interfaces: single-beat reads and writes, strobes, responses and interconnect routing.
VIPAIPTransactorAMBA AXI-Stream
On-chip interconnectAXI4-Stream · AXI5-Stream
Streaming sources and sinks with back-pressure, packet boundaries, sparse and null bytes, and routing by TID and TDEST.
VIPAIPTransactorAMBA ACE
On-chip interconnectACE · ACE-Lite · ACE5 · ACE5-Lite
Coherent AXI with snoop channels, cache-line states and barrier transactions, checked against the ACE coherency rules.
VIPAIPTransactorAMBA CHI
On-chip interconnectAMBA 5 CHI
Request, home and subordinate nodes for the Coherent Hub Interface: flits, credits, coherence transactions, cache states and retry.
VIPAIPTransactorAMBA AHB
On-chip interconnectAHB · AHB-Lite · AHB5
Managers, subordinates and bus fabrics for AHB: pipelined transfers, bursts, wait states, split and retry, and AHB5 secure and exclusive transfers.
VIPAIPTransactorAMBA APB
On-chip interconnectAPB2 · APB3 · APB4 · APB5
Peripheral bus requesters and completers with wait states, error responses, protection and strobes, and APB5 wake-up and parity.
VIPAIPTransactorAMBA ATB
On-chip interconnectATB (AMBA 3, 4, 5)
Trace bus masters and slaves: trace IDs, byte counts, flush requests and the synchronization behaviour of debug trace infrastructure.
VIPAIPTransactorAMBA CXS
On-chip interconnectCXS issues A–D · CXS-Lite
Credited streaming between a coherent interconnect and a chip-to-chip link: flits, credit exchange, link activation and deactivation.
VIPAIPTransactorAMBA Low Power Interface
On-chip interconnectQ-Channel · P-Channel
Power and clock controllers and devices on the Q-Channel and P-Channel handshakes: requests, accepts, denials and active signalling.
VIPAIPTransactorTileLink
On-chip interconnectTL-UL · TL-UH · TL-C
The open RISC-V chip interconnect: uncached lightweight and heavyweight operations and the cached TL-C conformance level with probes and grants.
VIPAIPTransactorOpen Core Protocol
On-chip interconnectOCP 2.x · 3.0
Configurable core-to-interconnect sockets: posted and non-posted writes, bursts, threads, tags and sideband signals.
VIPAIPTransactorAvalon
On-chip interconnectAvalon-MM · Avalon-ST
Memory-mapped and streaming interfaces used on Intel FPGAs: pipelined and burst reads, wait requests, packets and ready latency.
VIPAIPWishbone
On-chip interconnectB3 · B4 (classic and pipelined)
The open-source bus used across many free cores: classic and pipelined cycles, block and read-modify-write transfers, stalls and retries.
VIPTransactorVCI
On-chip interconnectPVCI · BVCI · AVCI
Peripheral, basic and advanced Virtual Component Interface: request and response packets, packet chaining and threads.
VIPTransactorNetwork-on-chip
On-chip interconnectAXI, CHI and custom endpoints
Traffic generators and checkers on every endpoint of a network-on-chip: routing, ordering, end-to-end data integrity, latency and bandwidth.
VIPPCI Express
PCIe, CXL and chipletsGen1 to Gen7 · Flit mode · PAM4
Root complex and endpoint models across the transaction, data link and physical layers, from 2.5 GT/s to 128 GT/s, including flit mode, FEC and L0p.
VIPTransactorPCIe switch
PCIe, CXL and chipletsGen3 to Gen7
Upstream and downstream ports around a PCIe switch: routing by address and ID, peer-to-peer traffic, ordering and error forwarding.
VIPPIPE
PCIe, CXL and chipletsPIPE 4.4 · 5.x · 6.x
The PHY Interface for PCI Express, SATA, USB and others: MAC and PHY models, original and SerDes architectures, message bus and rate changes.
VIPSR-IOV
PCIe, CXL and chipletsSingle Root I/O Virtualization
Physical and virtual functions on a PCIe device: VF enabling, routing IDs, per-function configuration space and function-level reset.
VIPPCIe ATS
PCIe, CXL and chipletsATS · PRI · PASID
Address Translation Services with an IOMMU model: translation requests and completions, invalidations, page requests and PASID.
VIPM-PCIe
PCIe, CXL and chipletsPCIe over M-PHY
PCI Express protocol layers over the MIPI M-PHY physical layer for low-power mobile links.
VIPPCI
PCIe, CXL and chipletsPCI 2.x · 3.0
Conventional parallel PCI initiators and targets: configuration, memory and I/O cycles, bursts, arbitration and parity.
VIPTransactorCompute Express Link
PCIe, CXL and chipletsCXL 1.1 · 2.0 · 3.x · 4.0
Host and device models for CXL.io, CXL.cache and CXL.mem on the PCIe physical layer: type 1, 2 and 3 devices, 68B and 256B flits, back-invalidation and memory pooling.
VIPCXL switch
PCIe, CXL and chipletsCXL 2.0 · 3.x
Ports around a CXL switch: virtual hierarchies, multi-logical devices, fabric routing and the fabric manager API.
VIPUCIe
PCIe, CXL and chipletsUCIe 1.1 · 2.0 · 3.0 · retimer
Die-to-die links for chiplets: the protocol, adapter and physical layers, standard and advanced packages, link training, sideband and retimers.
VIPBunch of Wires
PCIe, CXL and chipletsBoW 1.0 · 2.0
A simple open die-to-die interface for chiplets: slices, data and clock lanes, and link initialisation.
VIPUALink
PCIe, CXL and chipletsUALink 1.0
The open scale-up interconnect between AI accelerators: transaction, data link and physical layers, memory semantics and switch traffic.
VIPCCIX
PCIe, CXL and chipletsCCIX 1.x
Cache-coherent accelerator links over PCIe transport: request and snoop agents, home agents and port-to-port forwarding.
VIPOpenCAPI
PCIe, CXL and chipletsOpenCAPI 3.0 · 4.0
Coherent accelerator and memory attachment: transaction layer, data link layer and the host and device roles.
VIPTransactorGen-Z
PCIe, CXL and chipletsGen-Z core 1.x
Memory-semantic fabric requesters and responders: packets, routing, and the core specification's request and response classes.
VIPUSB 2.0
USBUSB 1.1 · 2.0 · OTG · UTMI+ · ULPI
Host, device and On-The-Go models at low, full and high speed: all transfer types, suspend and resume, link power management and PHY interfaces.
VIPUSB 3.2
USBUSB 3.0 · 3.1 · 3.2 · SSIC
SuperSpeed and SuperSpeedPlus hosts and devices up to 20 Gbps over two lanes: LTSSM, link commands, streams and power states.
VIPUSB4
USBUSB4 v1 · v2 (80 Gbps)
Routers, hosts and devices with tunnelled USB 3, DisplayPort and PCIe traffic, Gen 2, 3 and 4 links, PAM3 signalling and asymmetric mode.
VIPUSB hub
USBUSB 2.0 · 3.2 · USB4 hubs
Hub models with upstream and downstream ports: port status and control, transaction translation, and hub power management.
VIPUSB retimer
USBUSB 3.2 · USB4
Retimers on SuperSpeed and USB4 links: link training through the retimer, sideband transactions and the added latency.
VIPeUSB2
USBeUSB2 1.x · 2.0
Embedded USB 2.0 at low I/O voltage: native and repeater modes, control messages and the eUSB2 v2 higher-speed extensions.
VIPUSB Power Delivery
USBPD 3.0 · 3.1 · 3.2 (EPR)
Source, sink and cable plug models: BMC signalling on CC, power negotiation, extended power range, alternate modes and fast role swap.
VIPTransactorUSB Type-C
USBType-C 2.x
Connection detection on the CC pins: attach and detach, orientation, current advertisement, accessory modes and dual-role behaviour.
VIPxHCI
USBxHCI 1.2
The eXtensible Host Controller Interface from the software side: rings, transfer and command descriptors, events and doorbells.
VIPUSB Attached SCSI
USBUAS · UASP
SCSI commands over USB bulk streams: command, status and data pipes, task management and queued commands.
VIPDDR6
DRAMDDR6 (draft)
Device model for the next DDR generation, tracking the draft standard: sub-channels, commands, training and timing checks.
Memory modelDDR5
DRAMJESD79-5 · x4, x8, x16 · 3DS
DDR5 SDRAM device model with two sub-channels per DIMM channel, command and data training, refresh management, on-die ECC and every timing check.
AIPMemory modelTransactorDDR4
DRAMJESD79-4 · x4, x8, x16 · 3DS
DDR4 SDRAM device model: bank groups, write leveling, CRC and data bus inversion, gear-down, 3DS stacking and timing checks.
AIPMemory modelTransactorDDR3
DRAMJESD79-3 · DDR3L · 3DS
DDR3 and low-voltage DDR3L device models with write leveling, ZQ calibration, self-refresh and full timing checks.
AIPMemory modelTransactorDDR and DDR2
DRAMJESD79 · JESD79-2
First- and second-generation DDR SDRAM device models for legacy and long-lifetime designs.
AIPMemory modelTransactorLPDDR6
DRAMJESD209-6
LPDDR6 device model: 24-bit channels split into sub-channels, efficiency and power modes, training and timing checks.
Memory modelLPDDR5 and LPDDR5X
DRAMJESD209-5 · LPDDR5X
Low-power DRAM device models with WCK clocking, bank and bank-group modes, deep sleep, dynamic voltage and frequency scaling, and link ECC.
AIPMemory modelTransactorLPDDR4 and LPDDR4X
DRAMJESD209-4 · LPDDR4X
Two-channel low-power DRAM device models: command bus training, write leveling, frequency set points and power-down modes.
AIPMemory modelTransactorLPDDR, LPDDR2 and LPDDR3
DRAMLPSDR · LPDDR · LPDDR2 · LPDDR3
Earlier low-power DRAM generations for mobile and embedded designs that still ship them.
AIPMemory modelTransactorGDDR7
DRAMJESD239 · PAM3
Graphics DRAM device model with PAM3 signalling, four channels per device, error detection and correction, and training.
AIPMemory modelTransactorGDDR6 and GDDR6X
DRAMJESD250 · GDDR6X
Two-channel graphics DRAM device models: WCK clocking, read and write training, EDC and the x8 and x16 modes.
AIPMemory modelTransactorGDDR5 and GDDR5X
DRAMJESD212 · JESD232
Graphics DRAM device models with data bus inversion, address training and error detection codes.
AIPMemory modelTransactorGDDR2, GDDR3 and GDDR4
DRAMGDDR2 · GDDR3 · GDDR3L · GDDR4
Earlier graphics DRAM generations for long-lifetime designs.
Memory modelTransactorHBM4
DRAMJESD270-4 · SPHBM4
High Bandwidth Memory 4 stack model: 2048-bit interface, independent and pseudo channels, refresh management and ECC.
Memory modelHBM3 and HBM3E
DRAMJESD238 · HBM3E
Stacked DRAM models with pseudo channels, on-die ECC, error check and scrub, and the IEEE 1500 test port.
AIPMemory modelTransactorHBM and HBM2E
DRAMJESD235 A–D
First- and second-generation High Bandwidth Memory stacks: legacy and pseudo-channel modes, refresh and training.
AIPMemory modelTransactorDDR5 DIMM
DRAMUDIMM · RDIMM · LRDIMM · MRDIMM
Module models with the registering clock driver, data buffers, SPD hub and temperature sensors, and the multiplexed-rank MRDIMM.
Memory modelDDR4 DIMM
DRAMUDIMM · RDIMM · LRDIMM · 3DS · RCD · DB
DDR4 module models with the registering clock driver and data buffer as separate components.
Memory modelDDR3 DIMM
DRAMUDIMM · RDIMM · LRDIMM
DDR3 module models for legacy server and embedded designs.
Memory modelNVDIMM-P
DRAMJESD304
Non-volatile DIMM with the transactional protocol: asynchronous reads with IDs, persistent writes and flush.
Memory modelTransactorDFI
DRAMDFI 4.0 · 5.x · 6.0 · DDR, LPDDR, GDDR, HBM, ONFI
The DDR PHY Interface between memory controller and PHY: command, write and read data, update, low-power and training interfaces, in MC and PHY roles.
VIPAIPTransactorSDR SDRAM
DRAMJESD21-C
Single-data-rate synchronous DRAM device models with mode registers, bursts, auto and self-refresh.
AIPMemory modelTransactorRLDRAM
DRAMRLDRAM · RLDRAM 2 · RLDRAM 3 · LLDRAM
Reduced and low-latency DRAM for networking: SRAM-like addressing, short random-access cycles and multiplexed address modes.
Memory modelTransactorHybrid Memory Cube
DRAMHMC 1.x · 2.x
Packetized stacked-memory links: requests and responses, flow control, retry and vault addressing.
Memory modelTransactorWide I/O
DRAMWide I/O · Wide I/O 2
Through-silicon-via stacked mobile DRAM with wide, low-frequency channels.
Memory modelTransactorLegacy DRAM
DRAMEDO · FCRAM · RDRAM · SGRAM · VRAM · MDRAM
Older DRAM types kept alive in long-lifetime industrial, aerospace and replacement designs.
Memory modelTransactorONFI NAND
Flash, SRAM and other memoryONFI 4.x · 5.x · 6.0
Open NAND Flash Interface device models: SDR, NV-DDR2 and NV-DDR3 interfaces, multi-plane operations, cache and copy-back.
Memory modelTransactorNAND flash
Flash, SRAM and other memorySLC · MLC · Toggle mode
Raw NAND device models with page program, block erase, bad blocks, status polling and Toggle-mode DDR interfaces.
Memory modelTransactorSPI NAND
Flash, SRAM and other memorySingle · dual · quad
Serial NAND devices with internal ECC, page buffers and the SPI command set.
Memory modelSerial NOR flash
Flash, SRAM and other memorySPI · QSPI · Octal · Twin Quad · SFDP
Serial NOR models for boot and code storage: SFDP tables, quad and octal DTR reads, XIP, erase and program suspend.
Memory modelTransactorParallel NOR flash
Flash, SRAM and other memoryCFI · page and burst modes
Parallel NOR devices with CFI query, page and burst reads, sectors, and wide-supply variants.
Memory modelTransactorXccela
Flash, SRAM and other memoryXccela flash · Xccela PSRAM
Octal DDR devices on the Xccela bus for fast code execution and low-pin-count RAM.
Memory modelHyperBus
Flash, SRAM and other memoryHyperFlash · HyperRAM · Octal xSPI
Low-pin-count DDR memories on HyperBus: latency configuration, burst wrap and hybrid sleep.
Memory modelTransactorPSRAM
Flash, SRAM and other memoryAsync · page · burst · OctaRAM · CellularRAM
Pseudo-static RAM with hidden refresh, in asynchronous, page, burst and octal variants.
Memory modelSRAM
Flash, SRAM and other memoryAsync · synchronous · burst · ZBT
Asynchronous, synchronous and synchronous-burst SRAM device models with byte writes and timing checks.
Memory modelQDR SRAM
Flash, SRAM and other memoryQDR II · QDR II+ · QDR IV
Quad-data-rate SRAM with separate read and write ports, burst lengths and QDR IV's two bidirectional ports.
Memory modelTransactorTCAM
Flash, SRAM and other memoryTernary content-addressable memory
Ternary CAM models for lookup tables: match, mask, priority encoding and table updates.
Memory modelTransactorMRAM
Flash, SRAM and other memoryParallel · serial · DDR
Magnetoresistive RAM device models: non-volatile, byte-addressable and without erase cycles.
Memory modelTransactorFRAM
Flash, SRAM and other memoryParallel · SPI · I2C
Ferroelectric RAM models with fast non-volatile writes on parallel and serial interfaces.
Memory modelnvSRAM
Flash, SRAM and other memoryParallel · SPI
SRAM with a non-volatile shadow: autostore on power loss and recall on power-up.
Memory modelReRAM
Flash, SRAM and other memorySerial · parallel
Resistive RAM device models for low-power non-volatile storage.
Memory modelPhase-change memory
Flash, SRAM and other memoryParallel · serial
Phase-change memory device models with bit-alterable writes on parallel and serial interfaces.
Memory modelNVMe
StorageNVMe 1.4 · 2.0 · 2.1 · 2.2 · 2.3
Host and controller models over PCIe: admin and I/O queues, command sets including zoned and key-value, namespaces and interrupts.
VIPUFS
StorageUFS 3.1 · 4.x · 5.0
Universal Flash Storage host and device: UFS transport protocol over MIPI UniPro and M-PHY, task management, logical units and power modes.
VIPTransactoreMMC
StorageeMMC 4.5 · 5.0 · 5.1
Embedded MultiMediaCard host and device: HS200 and HS400 timing, command queuing, boot partitions and replay-protected memory.
VIPTransactorSD card
StorageSDHC · SDXC · SDUC · UHS-I, II, III · SD Express
SD hosts and cards across bus speeds and capacities, the UHS-II serial interface and SD Express over PCIe and NVMe.
VIPTransactorSDIO
StorageSDIO 3.0 · 4.0 · UHS-II
SD input/output cards for wireless and peripheral modules: function registers, block transfers and interrupts.
VIPTransactorSATA
StorageSATA 1.5, 3, 6 Gb/s · 3.x
Hosts and devices with OOB signalling, link and transport layers, native command queuing and power management.
VIPTransactorSAS
StorageSAS-2 · SAS-3 · SAS-4
Serial Attached SCSI initiators, targets and expanders: SSP, STP and SMP protocols and speed negotiation.
VIPTransactorFibre Channel
StorageFC-PI to FC-4 · FCoE
Fibre Channel ports and Fibre Channel over Ethernet: framing, login, classes of service and flow control.
VIPTransactorCompactFlash
StorageCF 4.x · 6.0
CompactFlash hosts and cards in memory, I/O and True IDE modes.
VIPEthernet 10M to 1G
Ethernet and networkingMII · RMII · SMII · GMII · RGMII · SGMII · TBI
MAC and PHY side models for 10 Mb/s to 1 Gb/s: the media-independent interfaces, 8b/10b PCS, auto-negotiation and frame checks.
VIPTransactorEthernet BASE-T
Ethernet and networking10/100/1000BASE-T · 2.5G and 5GBASE-T
Twisted-pair PHY behaviour: auto-negotiation, energy-efficient Ethernet and the 2.5G and 5G BASE-T rates.
VIPEthernet 10G
Ethernet and networkingXGMII · XAUI · 10GBASE-R, KR, KX4 · WIS
10 Gb/s MAC and PCS: XGMII and XAUI, 64b/66b coding, backplane training, FEC and the WAN interface sublayer.
VIPTransactorEthernet 25G and 50G
Ethernet and networking25GBASE-R, KR · 50GBASE-R, KR, KR2
25 and 50 Gb/s links with Reed-Solomon and BASE-R FEC, PAM4 single lanes and link training.
VIPTransactorEthernet 40G and 100G
Ethernet and networkingXLGMII · CGMII · KR4, CR4, SR4, LR4 · KR10
Multi-lane 40 and 100 Gb/s PCS with lane alignment markers, multi-lane distribution and RS-FEC.
VIPTransactorEthernet 200G and 400G
Ethernet and networking200GBASE-KR2, KR4, KR8 · 400GBASE-KR4, KR8, KR16
200 and 400 Gb/s MAC and PCS with RS(544,514) FEC, PAM4 lanes and flexible lane counts.
VIPTransactorEthernet 800G
Ethernet and networking800GBASE-R
800 Gb/s MAC and PCS on 100 Gb/s lanes with the FEC and lane structure of 800G Ethernet.
VIPEthernet 1.6T
Ethernet and networking1.6TBASE-R (draft)
1.6 Tb/s Ethernet on 200 Gb/s lanes, tracking the IEEE 802.3dj work.
VIPUltra Ethernet
Ethernet and networkingUEC 1.0
Ethernet transport for AI and HPC clusters: packet delivery sublayer, congestion control, semantic sublayer and link-level retry.
VIPTime-Sensitive Networking
Ethernet and networkingQbv · Qbu and 802.3br · Qav · Qci · Qbb PFC · CB · AVB
Deterministic Ethernet: time-aware shaping, frame preemption, credit-based shaping, per-stream filtering, redundancy and queue and forward behaviour.
VIPPTP and gPTP
Ethernet and networkingIEEE 1588-2019 · 802.1AS-2020
Precision time protocol masters and slaves: sync and follow-up messages, peer delay, timestamps and best master clock selection.
VIPMACsec
Ethernet and networking802.1AE · GCM-AES-128/256 · XPN
Link-layer security: secure channels and associations, GCM-AES encryption and integrity, replay protection and extended packet numbering.
VIPIPsec
Ethernet and networkingESP · AH · tunnel and transport
IP security packet processing: ESP and AH, tunnel and transport modes, security associations and anti-replay.
VIPTCP/IP
Ethernet and networkingIPv4 · IPv6 · TCP · UDP
Traffic and checking for TCP/IP offload engines: connection setup and teardown, segmentation, retransmission and checksums.
VIPRoCE
Ethernet and networkingRoCE v1 · v2
RDMA over Converged Ethernet: queue pairs, RDMA reads, writes and sends, acknowledgements and congestion notification.
VIPInterlaken
Ethernet and networkingInterlaken 1.2 · Look-Aside
Chip-to-chip packet interface: bursts and channels, in-band flow control, 64b/67b framing and lane striping.
VIPTransactorRapidIO
Ethernet and networkingRapidIO 2.x · 3.x · 4.x
Serial RapidIO endpoints and switches: logical, transport and physical layers, doorbells, messages and maintenance packets.
VIPTransactorCPRI
Ethernet and networkingCPRI 7.0
Radio equipment control and radio equipment links: hyperframes, IQ data, control and management channels and line rates.
VIPTransactoreCPRI
Ethernet and networkingeCPRI 2.0
Packet-based fronthaul over Ethernet or IP: message types, real-time control and remote memory access.
VIPO-RAN fronthaul
Ethernet and networkingControl, user and synchronisation planes
Open RAN fronthaul between distributed and radio units: C-plane and U-plane messages, sections and compression.
VIPOBSAI
Ethernet and networkingRP3 · RP3-01
Open Base Station Architecture reference point 3 links: message frames, line rates and synchronisation.
VIPTransactorRadio over Ethernet
Ethernet and networkingIEEE 1914.3
Encapsulation of radio data over Ethernet: structure-agnostic and structure-aware mappers and control packets.
VIPG.999.1
Ethernet and networkingG.999.1
The interface between link and PHY layers in multi-line DSL equipment: framing and stream identification.
VIPEtherCAT
Ethernet and networkingIEC 61158 type 12
Industrial Ethernet with on-the-fly processing: datagrams, distributed clocks and mailbox protocols.
TransactorMIPI CSI-2
MIPICSI-2 up to v4.x · D-PHY · C-PHY
Camera serial interface transmitters and receivers: virtual channels, data types, packet ECC and CRC, compression and always-on sensing.
VIPTransactorMIPI CSI-3
MIPICSI-3 over UniPro and M-PHY
Camera interface on the UniPro stack: attribute access, image streaming and camera control.
VIPTransactorMIPI DSI
MIPIDSI 1.3
Display serial interface hosts and peripherals: video and command modes, DCS commands, bus turnaround and ECC.
VIPTransactorMIPI DSI-2
MIPIDSI-2 up to v2.2 · D-PHY · C-PHY
Display serial interface on D-PHY and C-PHY: display stream compression, partial updates and higher resolutions.
VIPTransactorMIPI D-PHY
MIPID-PHY up to v3.5 · PPI
Clock-forwarded differential PHY: high-speed and low-power modes, escape mode, skew calibration and the PPI interface.
VIPMIPI C-PHY
MIPIC-PHY 2.x · 3.x
Three-phase symbol-encoded PHY on trios: symbol mapping, embedded clock, preambles and low-power states.
VIPMIPI M-PHY
MIPIM-PHY 4.x · 5.0 · 6.0 · RMMI
Serial PHY for UniPro, UFS and others: HS gears, PWM mode, line states, bursts and attribute configuration.
VIPTransactorMIPI A-PHY
MIPIA-PHY 1.x · PAL
Long-reach automotive SerDes for cameras and displays: packet retransmission, asymmetric links and the protocol adaptation layers.
VIPMIPI MASS
MIPIAutomotive SerDes Solutions
The MIPI automotive SerDes framework end to end: CSI-2 and DSI-2 over A-PHY with security and functional-safety service extensions.
VIPMIPI UniPro
MIPIUniPro 1.8 · 2.0 · 3.0
Layered transport over M-PHY: PHY adapter, data link with retransmission, network and transport layers, power-mode changes.
VIPTransactorMIPI I3C
MIPII3C 1.1.1 · 1.2 · I3C Basic
Controllers and targets with dynamic addressing, in-band interrupts, HDR modes, hot-join and mixed buses with legacy I2C devices.
VIPTransactorPSVMIPI RFFE
MIPIRFFE 2.x · 3.0
Control bus for RF front-end modules: register and extended-register commands, triggers and multiple masters.
VIPTransactorPSVMIPI SPMI
MIPISPMI 2.0
System power management interface between processors and power ICs: arbitration, register commands and multiple masters.
VIPTransactorPSVMIPI SoundWire
MIPISoundWire 1.2 · SoundWire I3S
Two-wire audio bus for codecs, amplifiers and microphones: frame shapes, data ports, bank switching and the SoundWire I3S variant.
VIPTransactorPSVMIPI SLIMbus
MIPISLIMbus 2.0
Serial low-power inter-chip media bus: message and data channels, clock gears and device enumeration.
VIPTransactorMIPI Debug
MIPISTP · TWP · SPP · HTI · Debug UART · Gigabit Debug for USB
Debug and trace transports: the system trace protocol, trace wrapper, parallel and high-speed trace ports, and debug over UART and USB.
VIPTransactorMIPI DBI and DPI
MIPIDBI-2 · DPI-2
Parallel and serial display bus and pixel interfaces for small displays: command access and pixel timing.
VIPMIPI HSI
MIPIHSI 1.x
High-speed synchronous serial link between application and cellular processors: channels, flow control and frame modes.
VIPMIPI LLI
MIPILLI 2.0
Low-latency interface for sharing memory between chips over M-PHY: low-latency and best-effort traffic classes.
VIPMIPI BIF
MIPIBIF 1.x
Single-wire battery interface between a mobile device and smart batteries: bus commands, addressing and interrupts.
VIPMIPI DigRF
MIPIDigRF v4
Digital interface between baseband and RF transceivers: data and control frames over M-PHY.
VIPMIPI VGI
MIPIVirtual GPIO
General-purpose I/O states carried as messages over a serial link instead of dedicated pins.
VIPDisplayPort
Display and videoDP 1.4 · 2.0 · 2.1 · MST · LTTPR
Sources, sinks and branch devices: link training, main-link transport, AUX channel, multi-stream, DSC and link-training tunable repeaters.
VIPTransactorDisplayPort Automotive Extensions
Display and videoDP AE 1.0
Functional safety and security additions to DisplayPort for in-vehicle displays: frame integrity checks and protected channels.
VIPEmbedded DisplayPort
Display and videoeDP 1.4b · 1.5 · 2.0
Internal panel links: panel self-refresh, adaptive sync, power-saving features and the panel replay of newer versions.
VIPHDMI
Display and videoHDMI 1.4 · 2.0 · 2.1 · 2.2
Sources and sinks with TMDS and fixed-rate link signalling, data islands, InfoFrames, SCDC, audio and DSC.
VIPTransactorHDCP
Display and videoHDCP 1.4 · 2.3 · 2.4
Content protection on HDMI and DisplayPort: authentication, key exchange, locality check, repeaters and link encryption.
VIPMHL
Display and videoMHL 1 · 2 · 3
Mobile high-definition link: packed-pixel video over few wires, control bus and the MHL sideband channel.
VIPV-by-One
Display and videoV-by-One HS · US
Panel interface with embedded clock: lane mapping, clock-data recovery training and hot-plug.
VIPTransactorLVDS display
Display and videoLVDS · OpenLDI · FPD-Link
Low-voltage differential video links: pixel mapping across lanes and OpenLDI and FPD-Link formats.
VIPTransactorSMPTE SDI
Display and videoSD · HD · 3G · 6G · 12G-SDI
Broadcast serial digital video: line and frame structure, ancillary data, scrambling and the multi-link and higher rates.
VIPTransactorCoaXPress
Display and videoCXP 1.1 · 2.0 · 2.1
Machine-vision camera links over coax: stream packets, control channel, triggers and power over coax.
VIPCamera Link HS
Display and videoM and X protocols
Machine-vision camera interface with video, command and pulse messages and resend for error recovery.
VIPCamera parallel interface
Display and videoCPI · BT.656 timing
Parallel pixel buses from image sensors: sync signals, pixel formats and embedded timing codes.
VIPTransactorSLVS-EC
Display and videoSLVS-EC 2.0
Embedded-clock image sensor interface: packet structure, lane distribution and error correction.
VIPMPEG-2 transport stream
Display and videoSerial and parallel TS
Transport-stream sources and checkers: packets, PIDs, program tables, continuity counters and timing references.
VIPCAN and CAN FD
AutomotiveClassical CAN · CAN FD · ISO 11898-1:2015
Controllers and nodes on a shared bus: arbitration, bit timing, error confinement, flexible data rate and the CAN FD frame formats.
VIPTransactorCAN XL
AutomotiveCiA 610 · ISO 11898-1:2024
The third CAN generation: data fields up to 2048 bytes, higher data rates, SDU types and the PWM transceiver mode.
VIPLIN
AutomotiveLIN 2.x · ISO 17987
Commander and responder nodes: schedule tables, frame types, checksums, sleep and wake-up, and node configuration.
VIPTransactorFlexRay
AutomotiveFlexRay 3.0.1
Time-triggered vehicle network: static and dynamic segments, clock synchronisation, startup and dual channels.
VIPTransactorSENT
AutomotiveSAE J2716 · short and enhanced serial messages
Single-edge nibble transmission from sensors: calibration pulses, nibble timing, CRC and serial message channels.
VIPTransactorPSI5
AutomotivePSI5 2.x
Two-wire current-modulated sensor interface for airbags and powertrain: synchronous and asynchronous modes and frame formats.
VIPCXPI
AutomotiveISO 20794
Clock extension peripheral interface for body electronics: event and polling modes, PWM coding and sleep handling.
VIPAutomotive Ethernet
Automotive10BASE-T1S · 100BASE-T1 · 1000BASE-T1 · multi-gig
Single-pair vehicle Ethernet: PLCA multidrop at 10 Mb/s, point-to-point 100 Mb/s and 1 Gb/s links and their PCS behaviour.
VIPASA Motion Link
AutomotiveASA-ML 1.x
Asymmetric automotive SerDes for cameras, sensors and displays: downlink and uplink, retransmission and security.
VIPMicrosecond Channel
AutomotiveMSC
Fast serial link between microcontrollers and power stages: command and data frames and the upstream channel.
VIPSAE J1850
AutomotiveVPW · PWM
Legacy vehicle diagnostic bus in its variable pulse width and pulse width modulation forms.
VIPSafe-by-Wire Plus
AutomotiveISO 22896
Airbag squib and sensor bus: deployment commands, diagnostics and the safety-critical message set.
VIPSafeSPI
AutomotiveSafeSPI 1.0
SPI for automotive sensors with CRC-protected frames and in-frame responses.
VIPARINC 429
Aerospace and defenceARINC 429 · 419
Avionics data bus transmitters and receivers: 32-bit words, labels, SDI and SSM fields, high and low speeds, and the earlier 419 formats.
VIPTransactorARINC 664 (AFDX)
Aerospace and defenceARINC 664 part 7
Avionics full-duplex switched Ethernet: virtual links, bandwidth allocation gaps, redundancy management and integrity checking.
VIPARINC 708
Aerospace and defenceARINC 708 · 708A
Weather radar display bus: 1600-bit words, Manchester coding and the radar data format.
VIPARINC 825
Aerospace and defenceARINC 825
CAN for airborne systems: identifier structure, logical communication channels and node service protocols.
VIPTransactorARINC 818
Aerospace and defenceARINC 818-2 · 818-3
Avionics digital video bus: Fibre Channel framing of video, container headers and line synchronisation.
VIPMIL-STD-1553
Aerospace and defenceMIL-STD-1553B · notice 2
Bus controllers, remote terminals and monitors: command and status words, mode codes, broadcast and dual redundant buses.
VIPTransactorMIL-STD-1773
Aerospace and defenceMIL-STD-1773
The fibre-optic form of the 1553 command and response protocol.
VIPTransactorSpaceWire
Aerospace and defenceECSS-E-ST-50-12C · RMAP
Spacecraft data links and routers: data-strobe encoding, link start-up, time codes, wormhole routing and remote memory access.
VIPTransactorSpaceFibre
Aerospace and defenceECSS-E-ST-50-11C
Multi-gigabit spacecraft links: virtual channels, quality of service, retry and multi-lane operation.
VIPSerial FPDP
Aerospace and defenceVITA 17.1
Serial front panel data port for radar and sensor data: framing, flow control and copy modes.
VIPIEC 61162
Aerospace and defenceIEC 61162-1 · -2 · -450
Maritime navigation and radiocommunication data: sentence formats, talkers and listeners.
VIPI2C
Serial and peripheralStandard · Fast · Fast-mode Plus · High-speed · Ultra Fast
Controllers and targets: 7- and 10-bit addressing, clock stretching, arbitration between controllers, repeated starts and every speed mode.
VIPAIPTransactorSMBus
Serial and peripheralSMBus 2.0 · 3.x
System management bus hosts and devices: protocol commands, packet error checking, alerts, timeouts and address resolution.
VIPAIPTransactorPMBus
Serial and peripheralPMBus 1.3 · 1.4 · 1.5
Power management command set over SMBus: standard commands, data formats, group commands and zone operations.
VIPAIPTransactorAVSBus
Serial and peripheralAVSBus 1.4 · 2.0 · 2.1
Adaptive voltage scaling bus between processors and regulators: voltage and status commands and the status response.
VIPTransactorIPMB
Serial and peripheralIPMB 1.0
Intelligent platform management bus over I2C: request and response messages, sequence numbers and checksums.
VIPSPI
Serial and peripheralModes 0–3 · multi-target · EEPROM, flash, FRAM and RTC devices
Controllers, targets and common SPI device models: clock polarity and phase, word lengths, chip selects and daisy chains.
VIPAIPTransactorQuad, Octal and Hexa SPI
Serial and peripheralDual · Quad · Octal · Hexa · SDR and DDR
Multi-I/O SPI for memories and peripherals: command, address and data phases on wider buses, DDR and data strobe.
VIPxSPI
Serial and peripheralJESD251 · profiles 1.0 and 2.0
Expanded SPI for non-volatile memory: octal DDR, the two command profiles and SFDP discovery.
VIPTransactoreSPI
Serial and peripheraleSPI 1.0 · 1.5
Enhanced SPI between chipset and embedded controller: peripheral, virtual wire, out-of-band and flash access channels.
VIPAIPTransactorLPC
Serial and peripheralLPC 1.1
Low pin count bus: memory, I/O and firmware cycles, DMA and bus mastering, and serial IRQ.
VIPAIPTransactorUART and USART
Serial and peripheral16550 · RS-232 · RS-485 · IrDA · synchronous mode
Asynchronous and synchronous serial ports: baud rates, framing, parity, flow control and break and error conditions.
VIPAIPTransactorJTAG
Serial and peripheralIEEE 1149.1 · 1149.6 · 1149.7 (cJTAG)
Test access port controllers and devices: TAP state machine, instruction and data registers, boundary scan, AC-coupled test and two-pin compact JTAG.
VIPAIPTransactorSerial Wire Debug
Serial and peripheralSWD v1 · v2 (multi-drop)
Two-pin debug access: packet requests, acknowledgements, parity, line reset and multi-drop target selection.
VIPJESD204
Serial and peripheralJESD204B · C · D
Serial links between data converters and logic: lane alignment, deterministic latency, 8b/10b, 64b/66b and the JESD204D coding.
VIPTransactorJESD207
Serial and peripheralJESD207
Parallel interface between baseband processors and RF transceivers: data bursts and control.
VIPTransactorJESD403 sideband bus
Serial and peripheralJESD403-1
The sideband bus on memory modules, based on I3C Basic: SPD hub, temperature sensors and module management.
VIPGPIO and SGPIO
Serial and peripheralGPIO · SGPIO (SFF-8485)
General-purpose I/O drivers and monitors, and the serial GPIO bus used for storage enclosure indicators.
VIPTimers, PWM and watchdog
Serial and peripheralPWM · PIT · WDT · RTC
Checkers and stimulus for timer peripherals: PWM duty and period, interval timers, watchdog timeouts and real-time clocks.
VIPSmart card
Serial and peripheralISO 7816-3 · SIM · USIM
Card readers and cards: answer to reset, T=0 and T=1 protocols, protocol and parameter selection, and SIM and USIM behaviour.
VIPTransactorSingle Wire Protocol
Serial and peripheralETSI TS 102 613
The link between an NFC controller and a SIM: S1 and S2 signalling and the data link frames.
VIPNFC
Serial and peripheralISO 14443 A and B · NFC-A, B, F
Proximity readers and tags: modulation and coding, anticollision, activation and the transmission protocol.
VIPTransactor1-Wire
Serial and peripheralStandard and overdrive speed
Single-wire bus with parasitic power: reset and presence, ROM commands and device search.
VIPMicrowire
Serial and peripheralMicrowire · Microwire/Plus
Three-wire serial interface for EEPROMs and peripherals.
VIPTransactorDALI
Serial and peripheralDALI-2 · IEC 62386
Digital lighting control: forward and backward frames, addressing, commands and timing.
VIPTransactorDMX512
Serial and peripheralDMX512-A · RDM
Stage lighting control over RS-485: break, mark-after-break, slots and remote device management.
VIPTransactorBiSS and SSI
Serial and peripheralBiSS-C · SSI
Encoder interfaces for motion control: synchronous serial position data, control frames and CRC.
VIPTPM interface
Serial and peripheralTPM 2.0 over SPI, I2C and LPC
The platform interface to a Trusted Platform Module: locality, register access and command and response flow.
VIPQi wireless power
Serial and peripheralQi 1.3 · 2.0
Communication between wireless chargers and receivers: packets, power transfer contracts and foreign object detection messages.
VIPI2S
AudioI2S · left- and right-justified
Audio serial ports: word select, sample widths, justification and controller or target clocking.
VIPTransactorTDM audio
AudioTDM 2 to 16 slots
Time-division multiplexed audio with many channels on one data line: slot widths, frame sync and offsets.
VIPTransactorPDM
AudioMono and stereo
Pulse-density modulated audio from digital microphones: clocking, stereo on shared lines and decimation checks.
VIPTransactorS/PDIF
AudioIEC 60958 · IEC 61937
Digital audio interface: biphase-mark coding, subframes and blocks, channel status and compressed audio payloads.
VIPTransactorRISC-V core
Processor and codingRV32 · RV64 · standard extensions
Core verification against an instruction-set reference model: random instruction streams, trace comparison, interrupts and exceptions.
VIPRISC-V PLIC
Processor and codingPLIC 1.0
Platform-level interrupt controller: priorities, thresholds, claim and complete, and per-hart contexts.
VIPFloating-point unit
Processor and codingIEEE 754-2019 · half, single, double
Floating-point operations checked against a reference: rounding modes, exceptions, subnormals, NaN handling and fused multiply-add.
VIPLine coding
Processor and coding8b/10b · 64b/66b · 128b/130b · 128b/132b
Encoders and decoders for serial links: disparity, control symbols, block sync, scrambling and error injection.
VIP
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