DRAM verification IP.
Lumina VIP for 26 protocols in DRAM: verification IP, assertion IP, memory models and synthesizable transactors, built for Lumina. DDR, LPDDR, GDDR and HBM devices, modules and DFI.
DDR6
DDR6 (draft)
Device model for the next DDR generation, tracking the draft standard: sub-channels, commands, training and timing checks.
Memory modelDDR5
JESD79-5 · x4, x8, x16 · 3DS
DDR5 SDRAM device model with two sub-channels per DIMM channel, command and data training, refresh management, on-die ECC and every timing check.
AIPMemory modelTransactorDDR4
JESD79-4 · x4, x8, x16 · 3DS
DDR4 SDRAM device model: bank groups, write leveling, CRC and data bus inversion, gear-down, 3DS stacking and timing checks.
AIPMemory modelTransactorDDR3
JESD79-3 · DDR3L · 3DS
DDR3 and low-voltage DDR3L device models with write leveling, ZQ calibration, self-refresh and full timing checks.
AIPMemory modelTransactorDDR and DDR2
JESD79 · JESD79-2
First- and second-generation DDR SDRAM device models for legacy and long-lifetime designs.
AIPMemory modelTransactorLPDDR6
JESD209-6
LPDDR6 device model: 24-bit channels split into sub-channels, efficiency and power modes, training and timing checks.
Memory modelLPDDR5 and LPDDR5X
JESD209-5 · LPDDR5X
Low-power DRAM device models with WCK clocking, bank and bank-group modes, deep sleep, dynamic voltage and frequency scaling, and link ECC.
AIPMemory modelTransactorLPDDR4 and LPDDR4X
JESD209-4 · LPDDR4X
Two-channel low-power DRAM device models: command bus training, write leveling, frequency set points and power-down modes.
AIPMemory modelTransactorLPDDR, LPDDR2 and LPDDR3
LPSDR · LPDDR · LPDDR2 · LPDDR3
Earlier low-power DRAM generations for mobile and embedded designs that still ship them.
AIPMemory modelTransactorGDDR7
JESD239 · PAM3
Graphics DRAM device model with PAM3 signalling, four channels per device, error detection and correction, and training.
AIPMemory modelTransactorGDDR6 and GDDR6X
JESD250 · GDDR6X
Two-channel graphics DRAM device models: WCK clocking, read and write training, EDC and the x8 and x16 modes.
AIPMemory modelTransactorGDDR5 and GDDR5X
JESD212 · JESD232
Graphics DRAM device models with data bus inversion, address training and error detection codes.
AIPMemory modelTransactorGDDR2, GDDR3 and GDDR4
GDDR2 · GDDR3 · GDDR3L · GDDR4
Earlier graphics DRAM generations for long-lifetime designs.
Memory modelTransactorHBM4
JESD270-4 · SPHBM4
High Bandwidth Memory 4 stack model: 2048-bit interface, independent and pseudo channels, refresh management and ECC.
Memory modelHBM3 and HBM3E
JESD238 · HBM3E
Stacked DRAM models with pseudo channels, on-die ECC, error check and scrub, and the IEEE 1500 test port.
AIPMemory modelTransactorHBM and HBM2E
JESD235 A–D
First- and second-generation High Bandwidth Memory stacks: legacy and pseudo-channel modes, refresh and training.
AIPMemory modelTransactorDDR5 DIMM
UDIMM · RDIMM · LRDIMM · MRDIMM
Module models with the registering clock driver, data buffers, SPD hub and temperature sensors, and the multiplexed-rank MRDIMM.
Memory modelDDR4 DIMM
UDIMM · RDIMM · LRDIMM · 3DS · RCD · DB
DDR4 module models with the registering clock driver and data buffer as separate components.
Memory modelDDR3 DIMM
UDIMM · RDIMM · LRDIMM
DDR3 module models for legacy server and embedded designs.
Memory modelNVDIMM-P
JESD304
Non-volatile DIMM with the transactional protocol: asynchronous reads with IDs, persistent writes and flush.
Memory modelTransactorDFI
DFI 4.0 · 5.x · 6.0 · DDR, LPDDR, GDDR, HBM, ONFI
The DDR PHY Interface between memory controller and PHY: command, write and read data, update, low-power and training interfaces, in MC and PHY roles.
VIPAIPTransactorSDR SDRAM
JESD21-C
Single-data-rate synchronous DRAM device models with mode registers, bursts, auto and self-refresh.
AIPMemory modelTransactorRLDRAM
RLDRAM · RLDRAM 2 · RLDRAM 3 · LLDRAM
Reduced and low-latency DRAM for networking: SRAM-like addressing, short random-access cycles and multiplexed address modes.
Memory modelTransactorHybrid Memory Cube
HMC 1.x · 2.x
Packetized stacked-memory links: requests and responses, flow control, retry and vault addressing.
Memory modelTransactorWide I/O
Wide I/O · Wide I/O 2
Through-silicon-via stacked mobile DRAM with wide, low-frequency channels.
Memory modelTransactorLegacy DRAM
EDO · FCRAM · RDRAM · SGRAM · VRAM · MDRAM
Older DRAM types kept alive in long-lifetime industrial, aerospace and replacement designs.
Memory modelTransactor
Browse by category
- 16
On-chip interconnect
AMBA, TileLink, OCP and other buses inside a chip.
- 15
PCIe, CXL and chiplets
PCI Express, CXL, UCIe and other high-speed links.
- 10
USB
USB 2.0 to USB4, Power Delivery and Type-C.
- 26
DRAM
DDR, LPDDR, GDDR and HBM devices, modules and DFI.
- 16
Flash, SRAM and other memory
NAND, NOR, SRAM, PSRAM and non-volatile memories.
- 9
Storage
NVMe, UFS, eMMC, SD, SATA and SAS.
- 24
Ethernet and networking
Ethernet from 10 Mb/s to 1.6 Tb/s, TSN, security and fronthaul.
- 22
MIPI
Camera, display, PHY, control and debug interfaces.
- 14
Display and video
DisplayPort, HDMI, HDCP, SDI and camera links.
- 13
Automotive
CAN, LIN, FlexRay, SENT and automotive Ethernet and SerDes.
- 11
Aerospace and defence
ARINC, MIL-STD-1553, SpaceWire and SpaceFibre.
- 28
Serial and peripheral
I2C, SPI, UART, JTAG, SMBus, PMBus and more.
- 4
Audio
I2S, TDM, PDM and S/PDIF.
- 4
Processor and coding
RISC-V cores and interrupt controllers, floating point and line coding.
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