PCIe, CXL and chiplets verification IP.
Lumina VIP for 15 protocols in PCIe, CXL and chiplets: verification IP, assertion IP, memory models and synthesizable transactors, built for Lumina. PCI Express, CXL, UCIe and other high-speed links.
PCI Express
Gen1 to Gen7 · Flit mode · PAM4
Root complex and endpoint models across the transaction, data link and physical layers, from 2.5 GT/s to 128 GT/s, including flit mode, FEC and L0p.
VIPTransactorPCIe switch
Gen3 to Gen7
Upstream and downstream ports around a PCIe switch: routing by address and ID, peer-to-peer traffic, ordering and error forwarding.
VIPPIPE
PIPE 4.4 · 5.x · 6.x
The PHY Interface for PCI Express, SATA, USB and others: MAC and PHY models, original and SerDes architectures, message bus and rate changes.
VIPSR-IOV
Single Root I/O Virtualization
Physical and virtual functions on a PCIe device: VF enabling, routing IDs, per-function configuration space and function-level reset.
VIPPCIe ATS
ATS · PRI · PASID
Address Translation Services with an IOMMU model: translation requests and completions, invalidations, page requests and PASID.
VIPM-PCIe
PCIe over M-PHY
PCI Express protocol layers over the MIPI M-PHY physical layer for low-power mobile links.
VIPPCI
PCI 2.x · 3.0
Conventional parallel PCI initiators and targets: configuration, memory and I/O cycles, bursts, arbitration and parity.
VIPTransactorCompute Express Link
CXL 1.1 · 2.0 · 3.x · 4.0
Host and device models for CXL.io, CXL.cache and CXL.mem on the PCIe physical layer: type 1, 2 and 3 devices, 68B and 256B flits, back-invalidation and memory pooling.
VIPCXL switch
CXL 2.0 · 3.x
Ports around a CXL switch: virtual hierarchies, multi-logical devices, fabric routing and the fabric manager API.
VIPUCIe
UCIe 1.1 · 2.0 · 3.0 · retimer
Die-to-die links for chiplets: the protocol, adapter and physical layers, standard and advanced packages, link training, sideband and retimers.
VIPBunch of Wires
BoW 1.0 · 2.0
A simple open die-to-die interface for chiplets: slices, data and clock lanes, and link initialisation.
VIPUALink
UALink 1.0
The open scale-up interconnect between AI accelerators: transaction, data link and physical layers, memory semantics and switch traffic.
VIPCCIX
CCIX 1.x
Cache-coherent accelerator links over PCIe transport: request and snoop agents, home agents and port-to-port forwarding.
VIPOpenCAPI
OpenCAPI 3.0 · 4.0
Coherent accelerator and memory attachment: transaction layer, data link layer and the host and device roles.
VIPTransactorGen-Z
Gen-Z core 1.x
Memory-semantic fabric requesters and responders: packets, routing, and the core specification's request and response classes.
VIP
Browse by category
- 16
On-chip interconnect
AMBA, TileLink, OCP and other buses inside a chip.
- 15
PCIe, CXL and chiplets
PCI Express, CXL, UCIe and other high-speed links.
- 10
USB
USB 2.0 to USB4, Power Delivery and Type-C.
- 26
DRAM
DDR, LPDDR, GDDR and HBM devices, modules and DFI.
- 16
Flash, SRAM and other memory
NAND, NOR, SRAM, PSRAM and non-volatile memories.
- 9
Storage
NVMe, UFS, eMMC, SD, SATA and SAS.
- 24
Ethernet and networking
Ethernet from 10 Mb/s to 1.6 Tb/s, TSN, security and fronthaul.
- 22
MIPI
Camera, display, PHY, control and debug interfaces.
- 14
Display and video
DisplayPort, HDMI, HDCP, SDI and camera links.
- 13
Automotive
CAN, LIN, FlexRay, SENT and automotive Ethernet and SerDes.
- 11
Aerospace and defence
ARINC, MIL-STD-1553, SpaceWire and SpaceFibre.
- 28
Serial and peripheral
I2C, SPI, UART, JTAG, SMBus, PMBus and more.
- 4
Audio
I2S, TDM, PDM and S/PDIF.
- 4
Processor and coding
RISC-V cores and interrupt controllers, floating point and line coding.
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Tell us which protocols and versions you need. We also add protocols on request.
Lumina VIP
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- Product types: VIP, assertion IP, memory model, transactor
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