On-chip interconnect verification IP.
Lumina VIP for 16 protocols in On-chip interconnect: verification IP, assertion IP, memory models and synthesizable transactors, built for Lumina. AMBA, TileLink, OCP and other buses inside a chip.
AMBA AXI
AXI3 · AXI4 · AXI5
Manager, subordinate and interconnect models for the AXI family, with outstanding and out-of-order transactions, bursts, atomics and AXI5 extensions.
VIPAIPTransactorAMBA AXI-Lite
AXI4-Lite · AXI5-Lite
Register-style AXI-Lite traffic for control interfaces: single-beat reads and writes, strobes, responses and interconnect routing.
VIPAIPTransactorAMBA AXI-Stream
AXI4-Stream · AXI5-Stream
Streaming sources and sinks with back-pressure, packet boundaries, sparse and null bytes, and routing by TID and TDEST.
VIPAIPTransactorAMBA ACE
ACE · ACE-Lite · ACE5 · ACE5-Lite
Coherent AXI with snoop channels, cache-line states and barrier transactions, checked against the ACE coherency rules.
VIPAIPTransactorAMBA CHI
AMBA 5 CHI
Request, home and subordinate nodes for the Coherent Hub Interface: flits, credits, coherence transactions, cache states and retry.
VIPAIPTransactorAMBA AHB
AHB · AHB-Lite · AHB5
Managers, subordinates and bus fabrics for AHB: pipelined transfers, bursts, wait states, split and retry, and AHB5 secure and exclusive transfers.
VIPAIPTransactorAMBA APB
APB2 · APB3 · APB4 · APB5
Peripheral bus requesters and completers with wait states, error responses, protection and strobes, and APB5 wake-up and parity.
VIPAIPTransactorAMBA ATB
ATB (AMBA 3, 4, 5)
Trace bus masters and slaves: trace IDs, byte counts, flush requests and the synchronization behaviour of debug trace infrastructure.
VIPAIPTransactorAMBA CXS
CXS issues A–D · CXS-Lite
Credited streaming between a coherent interconnect and a chip-to-chip link: flits, credit exchange, link activation and deactivation.
VIPAIPTransactorAMBA Low Power Interface
Q-Channel · P-Channel
Power and clock controllers and devices on the Q-Channel and P-Channel handshakes: requests, accepts, denials and active signalling.
VIPAIPTransactorTileLink
TL-UL · TL-UH · TL-C
The open RISC-V chip interconnect: uncached lightweight and heavyweight operations and the cached TL-C conformance level with probes and grants.
VIPAIPTransactorOpen Core Protocol
OCP 2.x · 3.0
Configurable core-to-interconnect sockets: posted and non-posted writes, bursts, threads, tags and sideband signals.
VIPAIPTransactorAvalon
Avalon-MM · Avalon-ST
Memory-mapped and streaming interfaces used on Intel FPGAs: pipelined and burst reads, wait requests, packets and ready latency.
VIPAIPWishbone
B3 · B4 (classic and pipelined)
The open-source bus used across many free cores: classic and pipelined cycles, block and read-modify-write transfers, stalls and retries.
VIPTransactorVCI
PVCI · BVCI · AVCI
Peripheral, basic and advanced Virtual Component Interface: request and response packets, packet chaining and threads.
VIPTransactorNetwork-on-chip
AXI, CHI and custom endpoints
Traffic generators and checkers on every endpoint of a network-on-chip: routing, ordering, end-to-end data integrity, latency and bandwidth.
VIP
Browse by category
- 16
On-chip interconnect
AMBA, TileLink, OCP and other buses inside a chip.
- 15
PCIe, CXL and chiplets
PCI Express, CXL, UCIe and other high-speed links.
- 10
USB
USB 2.0 to USB4, Power Delivery and Type-C.
- 26
DRAM
DDR, LPDDR, GDDR and HBM devices, modules and DFI.
- 16
Flash, SRAM and other memory
NAND, NOR, SRAM, PSRAM and non-volatile memories.
- 9
Storage
NVMe, UFS, eMMC, SD, SATA and SAS.
- 24
Ethernet and networking
Ethernet from 10 Mb/s to 1.6 Tb/s, TSN, security and fronthaul.
- 22
MIPI
Camera, display, PHY, control and debug interfaces.
- 14
Display and video
DisplayPort, HDMI, HDCP, SDI and camera links.
- 13
Automotive
CAN, LIN, FlexRay, SENT and automotive Ethernet and SerDes.
- 11
Aerospace and defence
ARINC, MIL-STD-1553, SpaceWire and SpaceFibre.
- 28
Serial and peripheral
I2C, SPI, UART, JTAG, SMBus, PMBus and more.
- 4
Audio
I2S, TDM, PDM and S/PDIF.
- 4
Processor and coding
RISC-V cores and interrupt controllers, floating point and line coding.
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Lumina VIP
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