HyperBus Memory Model
Low-pin-count DDR memories on HyperBus: latency configuration, burst wrap and hybrid sleep.
HyperBus memory model
HyperBus is a low-pin-count DDR interface for HyperFlash and HyperRAM, used in microcontrollers, displays and automotive clusters.
Lumina VIP for HyperBus covers HyperFlash · HyperRAM · Octal xSPI, as published by Infineon. It comes as memory model and synthesizable transactor, built for Lumina, so the same components run in simulation and report their results in one place.
What the HyperBus VIP covers.
Device model
- Command-address words, read and write transactions with RWDS
- Read, write or program timing checked against the datasheet
- Status, protection and power-down behaviour
- Contents preloaded from and dumped to files
- Fixed and variable latency, wrapped and linear bursts
- Hybrid sleep and deep power-down
What it checks
- Command sets, status and busy behaviour
- Read, program and erase timing
- Protection, suspend and resume
- Content preloading and inspection
Memory model capabilities
- Part configurations selected by density, width and speed grade
- Every timing parameter checked, with the violated parameter named in the message
- Sparse storage, so large densities use little host memory
- Backdoor preload, peek, poke and dump of the contents
- Mode registers and power states modelled
- Configurable error injection on read data
Transactor capabilities
- Synthesizable RTL for FPGA prototypes and emulators
- A transaction-level interface, so tests move unchanged from simulation
- Protocol checkers and monitors that run at hardware speed
- Streaming and buffered modes for throughput
Why Lumina VIP.
- Fast HyperBus testbench bring-up: connect the agents, pick a test and run
- Every failure names the rule it broke and the transaction that broke it
- Protocol coverage merges with your design coverage in one database
- Readable SystemVerilog and UVM source your team can extend
- The same scenarios run in simulation, on FPGA and on silicon
- Runs natively in Lumina Sim, with no wrappers and no separate compile
- Results structured for engineers and AI agents alike
Verification components.
Each component works on its own or together with the others in one environment, in active or passive mode.
- 01Memory device model
- 02Passive monitor and timing checker
HyperBus products.
HyperBus memory model
Device models that behave like the memory part: commands, modes, refresh and every timing parameter checked.
Includes
- Configurable density, width, speed grade and timing
- Timing and protocol checks on every command
- Mode registers, training and power-down behaviour
- Backdoor access to preload and inspect memory contents
HyperBus synthesizable transactor
Synthesizable models of the protocol for FPGA prototyping and hardware-assisted verification, driven from the same tests as the VIP.
Includes
- Synthesizable RTL for the protocol's roles
- A transaction interface to software or a testbench
- Monitors and checkers that run at hardware speed
Test suite and coverage.
- Directed tests for each feature of the specification
- Constrained-random tests across configurations and traffic mixes
- Error-injection tests that check how the design recovers
- A functional coverage model mapped to the specification
- Regression lists ready to run in Lumina
Test focus for this protocol family
- Every command in the datasheet
- Program and erase timing and suspend
- Protection and status behaviour
- Power-up, reset and power-down
What you receive.
- Readable source of every component
- The test suite and its coverage model
- An example environment connected to a sample design
- User guide, integration guide and release notes
- Scripts to run the examples in Lumina
Where it is used.
- Boot and code storage
- SSD and embedded storage controllers
- Networking and industrial systems
Frequently asked questions.
What is Lumina VIP for HyperBus?
Lumina VIP for HyperBus is a set of verification products for designs that use HyperBus: memory model and synthesizable transactor. Low-pin-count DDR memories on HyperBus: latency configuration, burst wrap and hybrid sleep.
Which HyperBus versions does it support?
HyperFlash · HyperRAM · Octal xSPI, as published by Infineon. If you need another version or option, tell us which one.
Which verification components are included?
Memory device model and Passive monitor and timing checker. Each one can be used on its own or together with the others in one environment.
What language and methodology does it use?
The verification IP and models are written in SystemVerilog with UVM, as readable source your team can extend. The transactors are synthesizable RTL for FPGA prototyping and hardware-assisted verification.
How does it work with Lumina?
It runs in Lumina Sim beside your RTL. Protocol coverage merges into the same database as your own coverage, and every violation names the rule it broke and the transaction that broke it.
Which tests come with it?
Directed tests for each feature of the specification. Constrained-random tests across configurations and traffic mixes. Error-injection tests that check how the design recovers. A functional coverage model mapped to the specification. Regression lists ready to run in Lumina. For this protocol family the tests focus on: every command in the datasheet, program and erase timing and suspend, protection and status behaviour and power-up, reset and power-down.
What is delivered?
Readable source of every component. The test suite and its coverage model. An example environment connected to a sample design. User guide, integration guide and release notes. Scripts to run the examples in Lumina.
How can I get Lumina VIP for HyperBus?
Lumina VIP for HyperBus is in preview. Email hello@lumeeslab.com with the versions and product types you need.
Need VIP for a protocol?
Tell us which protocols and versions you need. We also add protocols on request.
Lumina VIP
hello@lumeeslab.comHelpful to include
- The protocols and versions
- Product types: VIP, assertion IP, memory model, transactor
- Your schedule