RISC-V core Verification IP
Core verification against an instruction-set reference model: random instruction streams, trace comparison, interrupts and exceptions.
RISC-V core verification IP
Verification for RISC-V processor cores: an instruction-set reference model compared with the core as it retires each instruction, plus random instruction streams.
Lumina VIP for RISC-V core covers RV32 · RV64 · standard extensions, as published by RISC-V International. It comes as verification IP, built for Lumina, so the same components run in simulation and report their results in one place.
What the RISC-V core VIP covers.
Reference model
- RV32 and RV64 base sets with M, A, F, D, C and other standard extensions
- Machine, supervisor and user privilege modes
- Trap, interrupt and CSR behaviour
Stimulus and checking
- Constrained-random instruction streams
- Lock-step comparison of registers, memory and CSRs at retirement
- Instruction and privilege coverage
What it checks
- Results compared with a reference model
- Exceptions and corner cases
- Random and directed streams
- Error injection
Verification IP capabilities
- Active and passive agents for every protocol role, set per instance
- Bus widths, timing and optional features set by parameters, and changeable while a test runs
- A sequence library from basic directed traffic to constrained-random stress
- Error injection, static or on the fly, with checks that the expected error was seen
- Protocol checks that run in real time, each tied to a rule of the specification
- Scoreboards that check data end to end
- Throughput, latency and utilisation statistics for each interface
- Callbacks at each stage for your own checks and stimulus
- UVM register model adapters for protocols that carry register access
- Transaction logs and messages linked to the waveform for debug
Why Lumina VIP.
- Fast RISC-V core testbench bring-up: connect the agents, pick a test and run
- Every failure names the rule it broke and the transaction that broke it
- Protocol coverage merges with your design coverage in one database
- Readable SystemVerilog and UVM source your team can extend
- Runs natively in Lumina Sim, with no wrappers and no separate compile
- Results structured for engineers and AI agents alike
Verification components.
Each component works on its own or together with the others in one environment, in active or passive mode.
- 01Instruction-set reference model
- 02Instruction stream generator
- 03Retirement monitor and comparator
RISC-V core products.
RISC-V core verification IP
UVM agents that drive and check a protocol in simulation, in every role the protocol defines.
Includes
- Active and passive UVM agents for each protocol role
- Configurable sequences, from directed to constrained-random
- Protocol checks that flag violations with a spec reference
- Functional coverage of the protocol's features
- Scoreboards and transaction logs readable by people and AI agents
Test suite and coverage.
- Directed tests for each feature of the specification
- Constrained-random tests across configurations and traffic mixes
- Error-injection tests that check how the design recovers
- A functional coverage model mapped to the specification
- Regression lists ready to run in Lumina
Test focus for this protocol family
- Random and directed instruction or operand streams
- Exceptions and corner cases
- Comparison with the reference model
- Error and fault injection
What you receive.
- Readable source of every component
- The test suite and its coverage model
- An example environment connected to a sample design
- User guide, integration guide and release notes
- Scripts to run the examples in Lumina
Where it is used.
- RISC-V processor cores
- Floating-point units
- Serial link encoders and decoders
Frequently asked questions.
What is Lumina VIP for RISC-V core?
Lumina VIP for RISC-V core is a set of verification products for designs that use RISC-V core: verification IP. Core verification against an instruction-set reference model: random instruction streams, trace comparison, interrupts and exceptions.
Which RISC-V core versions does it support?
RV32 · RV64 · standard extensions, as published by RISC-V International. If you need another version or option, tell us which one.
Which verification components are included?
Instruction-set reference model, Instruction stream generator and Retirement monitor and comparator. Each one can be used on its own or together with the others in one environment.
What language and methodology does it use?
The verification IP and models are written in SystemVerilog with UVM, as readable source your team can extend.
How does it work with Lumina?
It runs in Lumina Sim beside your RTL. Protocol coverage merges into the same database as your own coverage, and every violation names the rule it broke and the transaction that broke it.
Which tests come with it?
Directed tests for each feature of the specification. Constrained-random tests across configurations and traffic mixes. Error-injection tests that check how the design recovers. A functional coverage model mapped to the specification. Regression lists ready to run in Lumina. For this protocol family the tests focus on: random and directed instruction or operand streams, exceptions and corner cases, comparison with the reference model and error and fault injection.
What is delivered?
Readable source of every component. The test suite and its coverage model. An example environment connected to a sample design. User guide, integration guide and release notes. Scripts to run the examples in Lumina.
How can I get Lumina VIP for RISC-V core?
Lumina VIP for RISC-V core is in preview. Email hello@lumeeslab.com with the versions and product types you need.
Need VIP for a protocol?
Tell us which protocols and versions you need. We also add protocols on request.
Lumina VIP
hello@lumeeslab.comHelpful to include
- The protocols and versions
- Product types: VIP, assertion IP, memory model, transactor
- Your schedule