SLVS-EC Verification IP
Embedded-clock image sensor interface: packet structure, lane distribution and error correction.
SLVS-EC verification IP
SLVS-EC is a high-speed image sensor interface with an embedded clock, used by large and fast CMOS sensors.
Lumina VIP for SLVS-EC covers SLVS-EC 2.0, as published by JIIA. It comes as verification IP, built for Lumina, so the same components run in simulation and report their results in one place.
What the SLVS-EC VIP covers.
Protocol
- Packet headers, payload and ECC
- Lane distribution and 8b/10b coding
Checks and error injection
- Line rates and lane counts in scope
- Frame and line start and end codes
- ECC-protected payload and errors injected
Scenarios and options
- Frames compared with image files
What it checks
- Video timing and pixel formats
- Link training and auxiliary channels
- Audio and metadata packets
- Content protection and compression where defined
Verification IP capabilities
- Active and passive agents for every protocol role, set per instance
- Bus widths, timing and optional features set by parameters, and changeable while a test runs
- A sequence library from basic directed traffic to constrained-random stress
- Error injection, static or on the fly, with checks that the expected error was seen
- Protocol checks that run in real time, each tied to a rule of the specification
- Scoreboards that check data end to end
- Throughput, latency and utilisation statistics for each interface
- Callbacks at each stage for your own checks and stimulus
- UVM register model adapters for protocols that carry register access
- Transaction logs and messages linked to the waveform for debug
Why Lumina VIP.
- Fast SLVS-EC testbench bring-up: connect the agents, pick a test and run
- Every failure names the rule it broke and the transaction that broke it
- Protocol coverage merges with your design coverage in one database
- Readable SystemVerilog and UVM source your team can extend
- Runs natively in Lumina Sim, with no wrappers and no separate compile
- Results structured for engineers and AI agents alike
Verification components.
Each component works on its own or together with the others in one environment, in active or passive mode.
- 01Source
- 02Sink
- 03Passive monitor
SLVS-EC products.
SLVS-EC verification IP
UVM agents that drive and check a protocol in simulation, in every role the protocol defines.
Includes
- Active and passive UVM agents for each protocol role
- Configurable sequences, from directed to constrained-random
- Protocol checks that flag violations with a spec reference
- Functional coverage of the protocol's features
- Scoreboards and transaction logs readable by people and AI agents
Test suite and coverage.
- Directed tests for each feature of the specification
- Constrained-random tests across configurations and traffic mixes
- Error-injection tests that check how the design recovers
- A functional coverage model mapped to the specification
- Regression lists ready to run in Lumina
Test focus for this protocol family
- Video timings and formats across resolutions
- Link training and hot-plug
- Audio and metadata packets
- Link and coding errors
What you receive.
- Readable source of every component
- The test suite and its coverage model
- An example environment connected to a sample design
- User guide, integration guide and release notes
- Scripts to run the examples in Lumina
Where it is used.
- Monitors, TVs and laptops
- Broadcast and machine vision
- Automotive displays
Frequently asked questions.
What is Lumina VIP for SLVS-EC?
Lumina VIP for SLVS-EC is a set of verification products for designs that use SLVS-EC: verification IP. Embedded-clock image sensor interface: packet structure, lane distribution and error correction.
Which SLVS-EC versions does it support?
SLVS-EC 2.0, as published by JIIA. If you need another version or option, tell us which one.
Which verification components are included?
Source, Sink and Passive monitor. Each one can be used on its own or together with the others in one environment.
What language and methodology does it use?
The verification IP and models are written in SystemVerilog with UVM, as readable source your team can extend.
How does it work with Lumina?
It runs in Lumina Sim beside your RTL. Protocol coverage merges into the same database as your own coverage, and every violation names the rule it broke and the transaction that broke it.
Which tests come with it?
Directed tests for each feature of the specification. Constrained-random tests across configurations and traffic mixes. Error-injection tests that check how the design recovers. A functional coverage model mapped to the specification. Regression lists ready to run in Lumina. For this protocol family the tests focus on: video timings and formats across resolutions, link training and hot-plug, audio and metadata packets and link and coding errors.
What is delivered?
Readable source of every component. The test suite and its coverage model. An example environment connected to a sample design. User guide, integration guide and release notes. Scripts to run the examples in Lumina.
How can I get Lumina VIP for SLVS-EC?
Lumina VIP for SLVS-EC is in preview. Email hello@lumeeslab.com with the versions and product types you need.
Need VIP for a protocol?
Tell us which protocols and versions you need. We also add protocols on request.
Lumina VIP
hello@lumeeslab.comHelpful to include
- The protocols and versions
- Product types: VIP, assertion IP, memory model, transactor
- Your schedule