USB 3.2 Verification IP
SuperSpeed and SuperSpeedPlus hosts and devices up to 20 Gbps over two lanes: LTSSM, link commands, streams and power states.
USB 3.2 verification IP
USB 3.2 covers the SuperSpeed modes from 5 Gbps on one lane to 20 Gbps on two lanes. It runs alongside USB 2.0 on the same connector and adds its own link layer and power states.
Lumina VIP for USB 3.2 covers USB 3.0 · 3.1 · 3.2 · SSIC, as published by USB-IF. It comes as verification IP, built for Lumina, so the same components run in simulation and report their results in one place.
What the USB 3.2 VIP covers.
Link and physical layer
- Gen 1 (8b/10b) and Gen 2 (128b/132b), x1 and x2 lanes
- LTSSM, polling, recovery, hot reset and compliance mode
- Link commands, header packet retry and flow control credits
- U0 to U3 power states and LFPS signalling
Protocol layer
- Transaction, data and isochronous timestamp packets
- Bulk streams for UAS and burst transfers
- Function wake and latency tolerance messages
- SSIC: SuperSpeed over M-PHY
What it checks
- Enumeration, descriptors and every transfer type
- Link and power state machines
- Timing of packets, handshakes and turnarounds
- Error injection and recovery
Verification IP capabilities
- Active and passive agents for every protocol role, set per instance
- Bus widths, timing and optional features set by parameters, and changeable while a test runs
- A sequence library from basic directed traffic to constrained-random stress
- Error injection, static or on the fly, with checks that the expected error was seen
- Protocol checks that run in real time, each tied to a rule of the specification
- Scoreboards that check data end to end
- Throughput, latency and utilisation statistics for each interface
- Callbacks at each stage for your own checks and stimulus
- UVM register model adapters for protocols that carry register access
- Transaction logs and messages linked to the waveform for debug
Why Lumina VIP.
- Fast USB 3.2 testbench bring-up: connect the agents, pick a test and run
- Every failure names the rule it broke and the transaction that broke it
- Protocol coverage merges with your design coverage in one database
- Readable SystemVerilog and UVM source your team can extend
- Runs natively in Lumina Sim, with no wrappers and no separate compile
- Results structured for engineers and AI agents alike
Verification components.
Each component works on its own or together with the others in one environment, in active or passive mode.
- 01Host
- 02Device
- 03Passive monitor
USB 3.2 products.
USB 3.2 verification IP
UVM agents that drive and check a protocol in simulation, in every role the protocol defines.
Includes
- Active and passive UVM agents for each protocol role
- Configurable sequences, from directed to constrained-random
- Protocol checks that flag violations with a spec reference
- Functional coverage of the protocol's features
- Scoreboards and transaction logs readable by people and AI agents
Test suite and coverage.
- Directed tests for each feature of the specification
- Constrained-random tests across configurations and traffic mixes
- Error-injection tests that check how the design recovers
- A functional coverage model mapped to the specification
- Regression lists ready to run in Lumina
Test focus for this protocol family
- Enumeration for every device class in scope
- Each transfer type at each speed
- Link power management entry and exit
- Packet, CRC and timeout errors
What you receive.
- Readable source of every component
- The test suite and its coverage model
- An example environment connected to a sample design
- User guide, integration guide and release notes
- Scripts to run the examples in Lumina
Where it is used.
- PCs, docks and hubs
- Phones and tablets
- Chargers and Type-C controllers
Frequently asked questions.
What is Lumina VIP for USB 3.2?
Lumina VIP for USB 3.2 is a set of verification products for designs that use USB 3.2: verification IP. SuperSpeed and SuperSpeedPlus hosts and devices up to 20 Gbps over two lanes: LTSSM, link commands, streams and power states.
Which USB 3.2 versions does it support?
USB 3.0 · 3.1 · 3.2 · SSIC, as published by USB-IF. If you need another version or option, tell us which one.
Which verification components are included?
Host, Device and Passive monitor. Each one can be used on its own or together with the others in one environment.
What language and methodology does it use?
The verification IP and models are written in SystemVerilog with UVM, as readable source your team can extend.
How does it work with Lumina?
It runs in Lumina Sim beside your RTL. Protocol coverage merges into the same database as your own coverage, and every violation names the rule it broke and the transaction that broke it.
Which tests come with it?
Directed tests for each feature of the specification. Constrained-random tests across configurations and traffic mixes. Error-injection tests that check how the design recovers. A functional coverage model mapped to the specification. Regression lists ready to run in Lumina. For this protocol family the tests focus on: enumeration for every device class in scope, each transfer type at each speed, link power management entry and exit and packet, CRC and timeout errors.
What is delivered?
Readable source of every component. The test suite and its coverage model. An example environment connected to a sample design. User guide, integration guide and release notes. Scripts to run the examples in Lumina.
How can I get Lumina VIP for USB 3.2?
Lumina VIP for USB 3.2 is in preview. Email hello@lumeeslab.com with the versions and product types you need.
Need VIP for a protocol?
Tell us which protocols and versions you need. We also add protocols on request.
Lumina VIP
hello@lumeeslab.comHelpful to include
- The protocols and versions
- Product types: VIP, assertion IP, memory model, transactor
- Your schedule