Every core on the chip, in one emulation.

A modern SoC is a Cortex-A cluster, a real-time core, a security core and a power manager, often from two ISAs. CARME runs all of them together, each with its own firmware, on one time line.

RTL in the loop Boards and SoCs

carme · soc0running

uart0

*** Booting Zephyr OS ***

Arm M-profile
Cortex-M0, Cortex-M0+, Cortex-M3, Cortex-M4, Cortex-M4F, Cortex-M7, Cortex-M23, Cortex-M33, Cortex-M85, Cortex-M52, Cortex-M55, Cortex-M85 with Helium (MVE) · TrustZone-M, MPU, FPU, DSP, lockstep pairs
Arm R-profile
Cortex-R5F, Cortex-R8, Cortex-R52 · SMP and split-lock clusters, MPU, hypervisor (R52)
Arm A-profile, 32-bit
ARM926EJ-S, Cortex-A7, Cortex-A9, Cortex-A15 · SMP, TrustZone, VFP and NEON
Arm A-profile, 64-bit
Cortex-A53, Cortex-A55, Cortex-A78, Armv8-A generic, Cortex-A72, Cortex-A76, Armv9-A (Cortex-A520, Cortex-A720) · EL0 to EL3, GICv2 and GICv3, SMMUv3, SMP
RISC-V, 32-bit
Ibex, CV32E40P, RI5CY, PicoRV32, VexRiscv, Minerva, VeeR EL2, Andes N25, SiFive E31, generic RV32, Hazard3 · I, M, A, F, D, C, B and Zicsr, Zifencei; PMP; custom instructions
RISC-V, 64-bit
SiFive U54, SiFive U74, Kendryte K210, generic RV64GC, RVA23 profile, SiFive P550, T-Head C906, NOEL-V · S-mode and MMU, V 1.0 vector, SMP
SPARC V8
LEON3, LEON3FT, LEON4FT
Power Architecture
e200z6, Microwatt (64-bit POWER)
x86
Intel Quark, x86 (i386 to Atom N270), x86-64 · host-accelerated on Linux
Xtensa
Xtensa configurable core, Xtensa LX7
MSP430
MSP430X
TriCore
TriCore 1.6.2 (AURIX TC3xx)
Your own core
Any CPU in RTL, co-simulated in Lumina Sim · run firmware on the RTL of your own core, with the rest of the SoC emulated

Architecture	Cores	Notes
Arm M-profile	Cortex-M0, Cortex-M0+, Cortex-M3, Cortex-M4, Cortex-M4F, Cortex-M7, Cortex-M23, Cortex-M33, Cortex-M85, Cortex-M52, Cortex-M55, Cortex-M85 with Helium (MVE)	TrustZone-M, MPU, FPU, DSP, lockstep pairs
Arm R-profile	Cortex-R5F, Cortex-R8, Cortex-R52	SMP and split-lock clusters, MPU, hypervisor (R52)
Arm A-profile, 32-bit	ARM926EJ-S, Cortex-A7, Cortex-A9, Cortex-A15	SMP, TrustZone, VFP and NEON
Arm A-profile, 64-bit	Cortex-A53, Cortex-A55, Cortex-A78, Armv8-A generic, Cortex-A72, Cortex-A76, Armv9-A (Cortex-A520, Cortex-A720)	EL0 to EL3, GICv2 and GICv3, SMMUv3, SMP
RISC-V, 32-bit	Ibex, CV32E40P, RI5CY, PicoRV32, VexRiscv, Minerva, VeeR EL2, Andes N25, SiFive E31, generic RV32, Hazard3	I, M, A, F, D, C, B and Zicsr, Zifencei; PMP; custom instructions
RISC-V, 64-bit	SiFive U54, SiFive U74, Kendryte K210, generic RV64GC, RVA23 profile, SiFive P550, T-Head C906, NOEL-V	S-mode and MMU, V 1.0 vector, SMP
SPARC V8	LEON3, LEON3FT, LEON4FT
Power Architecture	e200z6, Microwatt (64-bit POWER)
x86	Intel Quark, x86 (i386 to Atom N270), x86-64	host-accelerated on Linux
Xtensa	Xtensa configurable core, Xtensa LX7
MSP430	MSP430X
TriCore	TriCore 1.6.2 (AURIX TC3xx)
Your own core	Any CPU in RTL, co-simulated in Lumina Sim	run firmware on the RTL of your own core, with the rest of the SoC emulated

What is modelled

The parts of the core your software depends on.

Privilege and isolation:Arm EL0 to EL3 and TrustZone, TrustZone-M, RISC-V M, S and U modes, PMP and MPU, MMUs with the page-table formats Linux uses.
Floating point and vector:VFP, NEON, Helium, RISC-V F, D and V 1.0.
Multicore:SMP clusters, asymmetric multiprocessing, lockstep pairs, shared and private memory, inter-processor interrupts.
Interrupt controllers:NVIC, GICv2 and GICv3, PLIC, CLINT, CLIC and AIA, with vendor-specific ones in the SoC models.

Your own instructions

Custom instructions at full speed.

RISC-V custom instructions and CSRs are described in a few lines and run at full speed, written in Python or backed by your RTL. Check what the compiler emits against what the hardware will do, before the core exists.

python

# a custom multiply-accumulate on custom-0
@cpu.instruction("0000000 ----- ----- 000 ----- 0001011")
def mac(cpu, rd, rs1, rs2):
    cpu.x[rd] = (cpu.x[rd] + cpu.x[rs1] * cpu.x[rs2]) & 0xFFFF_FFFF

Your own core, in RTL

Stop at the first instruction that differs.

Put your CPU's RTL in Lumina Sim and let CARME provide the rest of the system. Every retired instruction can be compared with CARME's reference model of the same ISA, and the run stops at the first difference.

crypto0 · aes_gcmrunning

CPU

AXI4

crypto0ModelRTL

def on_write_CTRL(p, v):
    if p.CTRL.START:
        p.DATA = aes_gcm(p.KEY, p.IN)
        p.STATUS.DONE = 1
        p.irq.done.pulse()

uart0: aes-gcm 1000 blocks OK

Questions

Common questions.

Can different ISAs run in one system?

Yes. An Arm application cluster, a RISC-V security core and an M-class power manager run together on one time line, each with its own firmware.

Can I add instructions to a core?

Yes. RISC-V custom instructions and CSRs are described in a few lines of Python, or backed by your RTL.

Full-system emulation for embedded and silicon teams

Bring the core, or the cluster of them.

Become a test partner RTL in the loop

Every core on the chip, in one emulation.

The parts of the core your software depends on.

Custom instructions at full speed.

Stop at the first instruction that differs.

Common questions.

Can different ISAs run in one system?

Can I add instructions to a core?

Full-system emulation for embedded and silicon teams

For embedded developers

For silicon teams

RTL in the loop

Lumina integration

Testing and CI

Boards and SoCs

Peripherals

Bring the core, or the cluster of them.

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