Avalon Verification IP
Memory-mapped and streaming interfaces used on Intel FPGAs: pipelined and burst reads, wait requests, packets and ready latency.
Avalon verification IP
Avalon is the interface family of Intel FPGA designs: Avalon-MM for memory-mapped access and Avalon-ST for streaming data, used throughout Platform Designer systems.
Lumina VIP for Avalon covers Avalon-MM · Avalon-ST, as published by Intel. It comes as verification IP and assertion IP, built for Lumina, so the same components run in simulation and formal proofs and report their results in one place.
What the Avalon VIP covers.
Avalon-MM
- Reads and writes with waitrequest and byte enables
- Pipelined reads with readdatavalid and burst transfers
- Fixed and variable latency, response status
Avalon-ST
- Ready latency and ready allowance
- Packets, empty symbols, channels and errors
Scenarios and options
- Avalon-MM host and agent, Avalon-ST source and sink
- Random waitrequest and ready back-pressure
What it checks
- Handshakes and channel ordering on every interface
- Outstanding, out-of-order and interleaved transactions
- Bursts, address alignment and data integrity end to end
- Response and error signalling, exclusive and atomic access
Verification IP capabilities
- Active and passive agents for every protocol role, set per instance
- Bus widths, timing and optional features set by parameters, and changeable while a test runs
- A sequence library from basic directed traffic to constrained-random stress
- Error injection, static or on the fly, with checks that the expected error was seen
- Protocol checks that run in real time, each tied to a rule of the specification
- Scoreboards that check data end to end
- Throughput, latency and utilisation statistics for each interface
- Callbacks at each stage for your own checks and stimulus
- UVM register model adapters for protocols that carry register access
- Transaction logs and messages linked to the waveform for debug
Assertion IP capabilities
- One assertion per protocol rule, named after the rule
- Assumptions that constrain inputs in formal and become checks in simulation
- Cover properties for each protocol scenario
- Parameters for widths and optional features
- The same properties run in formal proofs and in simulation
- Bind files that attach to your RTL without edits
Why Lumina VIP.
- Fast Avalon testbench bring-up: connect the agents, pick a test and run
- Every failure names the rule it broke and the transaction that broke it
- Protocol coverage merges with your design coverage in one database
- Readable SystemVerilog and UVM source your team can extend
- Assertion IP proves the protocol rules in Lumina Formal
- Runs natively in Lumina Sim, with no wrappers and no separate compile
- Results structured for engineers and AI agents alike
Verification components.
Each component works on its own or together with the others in one environment, in active or passive mode.
- 01Host (master) and agent (slave)
- 02Source and sink
- 03Passive monitor
Avalon products.
Avalon verification IP
UVM agents that drive and check a protocol in simulation, in every role the protocol defines.
Includes
- Active and passive UVM agents for each protocol role
- Configurable sequences, from directed to constrained-random
- Protocol checks that flag violations with a spec reference
- Functional coverage of the protocol's features
- Scoreboards and transaction logs readable by people and AI agents
Avalon assertion IP
SystemVerilog assertions, assumptions and cover properties that prove a design follows the protocol in Lumina Formal, or check it in simulation.
Includes
- Assertions for every protocol rule, each named after its rule
- Assumptions to constrain the inputs in formal proofs
- Cover properties for the protocol's scenarios
- Bind files for attaching to your design without edits
Test suite and coverage.
- Directed tests for each feature of the specification
- Constrained-random tests across configurations and traffic mixes
- Error-injection tests that check how the design recovers
- A functional coverage model mapped to the specification
- Regression lists ready to run in Lumina
Test focus for this protocol family
- Every burst type, size and length
- Outstanding and out-of-order traffic at the configured limits
- Exclusive, atomic and protection attributes
- Back-pressure and random ready and valid timing
What you receive.
- Readable source of every component
- The test suite and its coverage model
- An example environment connected to a sample design
- User guide, integration guide and release notes
- Scripts to run the examples in Lumina
Where it is used.
- SoC and subsystem interconnects
- Processor clusters and accelerators
- Peripheral and register buses
Frequently asked questions.
What is Lumina VIP for Avalon?
Lumina VIP for Avalon is a set of verification products for designs that use Avalon: verification IP and assertion IP. Memory-mapped and streaming interfaces used on Intel FPGAs: pipelined and burst reads, wait requests, packets and ready latency.
Which Avalon versions does it support?
Avalon-MM · Avalon-ST, as published by Intel. If you need another version or option, tell us which one.
Which verification components are included?
Host (master) and agent (slave), Source and sink and Passive monitor. Each one can be used on its own or together with the others in one environment.
What language and methodology does it use?
The verification IP and models are written in SystemVerilog with UVM, as readable source your team can extend. The assertion IP uses SystemVerilog Assertions, with bind files for attaching to your design.
How does it work with Lumina?
It runs in Lumina Sim beside your RTL, and the assertion IP proves your design in Lumina Formal. Protocol coverage merges into the same database as your own coverage, and every violation names the rule it broke and the transaction that broke it.
Which tests come with it?
Directed tests for each feature of the specification. Constrained-random tests across configurations and traffic mixes. Error-injection tests that check how the design recovers. A functional coverage model mapped to the specification. Regression lists ready to run in Lumina. For this protocol family the tests focus on: every burst type, size and length, outstanding and out-of-order traffic at the configured limits, exclusive, atomic and protection attributes and back-pressure and random ready and valid timing.
What is delivered?
Readable source of every component. The test suite and its coverage model. An example environment connected to a sample design. User guide, integration guide and release notes. Scripts to run the examples in Lumina.
How can I get Lumina VIP for Avalon?
Lumina VIP for Avalon is in preview. Email hello@lumeeslab.com with the versions and product types you need.
Need VIP for a protocol?
Tell us which protocols and versions you need. We also add protocols on request.
Lumina VIP
hello@lumeeslab.comHelpful to include
- The protocols and versions
- Product types: VIP, assertion IP, memory model, transactor
- Your schedule