DDR5 Memory Model
DDR5 SDRAM device model with two sub-channels per DIMM channel, command and data training, refresh management, on-die ECC and every timing check.
DDR5 memory model
DDR5 is the main memory of current servers and PCs. Each DIMM has two independent 32-bit sub-channels, devices carry on-die ECC, and power management moves onto the module.
Lumina VIP for DDR5 covers JESD79-5 · x4, x8, x16 · 3DS, as published by JEDEC. It comes as assertion IP, memory model and synthesizable transactor, built for Lumina, so the same components run in simulation and formal proofs and report their results in one place.
What the DDR5 VIP covers.
Commands and data
- Full command set, including write pattern, MPC and refresh management
- Burst lengths 8, 16 and 32, with burst chop
- x4, x8 and x16 devices, 3DS stacks and all speed grades
- Write CRC, read CRC and on-die ECC with error check and scrub
Training and calibration
- CS and CA training, read preamble training and write leveling
- Vref CA, CS and DQ training and ZQ calibration
- Programmable latencies, preambles and postambles
- Decision feedback equalization settings
Refresh and power
- All-bank and same-bank refresh, refresh management and adaptive and directed RFM
- Self-refresh with frequency change, power-down and maximum power saving mode
- Post package repair: hard, soft and memory BIST
- Every timing parameter checked on every command
What it checks
- Command sequences against every timing parameter
- Initialisation, training and mode-register settings
- Refresh, self-refresh and power-down rules
- Data integrity, ECC and CRC
Assertion IP capabilities
- One assertion per protocol rule, named after the rule
- Assumptions that constrain inputs in formal and become checks in simulation
- Cover properties for each protocol scenario
- Parameters for widths and optional features
- The same properties run in formal proofs and in simulation
- Bind files that attach to your RTL without edits
Memory model capabilities
- Part configurations selected by density, width and speed grade
- Every timing parameter checked, with the violated parameter named in the message
- Sparse storage, so large densities use little host memory
- Backdoor preload, peek, poke and dump of the contents
- Mode registers and power states modelled
- Configurable error injection on read data
Transactor capabilities
- Synthesizable RTL for FPGA prototypes and emulators
- A transaction-level interface, so tests move unchanged from simulation
- Protocol checkers and monitors that run at hardware speed
- Streaming and buffered modes for throughput
Why Lumina VIP.
- Fast DDR5 testbench bring-up: connect the agents, pick a test and run
- Every failure names the rule it broke and the transaction that broke it
- Protocol coverage merges with your design coverage in one database
- Readable SystemVerilog and UVM source your team can extend
- The same scenarios run in simulation, on FPGA and on silicon
- Assertion IP proves the protocol rules in Lumina Formal
- Runs natively in Lumina Sim, with no wrappers and no separate compile
- Results structured for engineers and AI agents alike
Verification components.
Each component works on its own or together with the others in one environment, in active or passive mode.
- 01Memory device model
- 02Passive monitor and timing checker
DDR5 products.
DDR5 assertion IP
SystemVerilog assertions, assumptions and cover properties that prove a design follows the protocol in Lumina Formal, or check it in simulation.
Includes
- Assertions for every protocol rule, each named after its rule
- Assumptions to constrain the inputs in formal proofs
- Cover properties for the protocol's scenarios
- Bind files for attaching to your design without edits
DDR5 memory model
Device models that behave like the memory part: commands, modes, refresh and every timing parameter checked.
Includes
- Configurable density, width, speed grade and timing
- Timing and protocol checks on every command
- Mode registers, training and power-down behaviour
- Backdoor access to preload and inspect memory contents
DDR5 synthesizable transactor
Synthesizable models of the protocol for FPGA prototyping and hardware-assisted verification, driven from the same tests as the VIP.
Includes
- Synthesizable RTL for the protocol's roles
- A transaction interface to software or a testbench
- Monitors and checkers that run at hardware speed
Test suite and coverage.
- Directed tests for each feature of the specification
- Constrained-random tests across configurations and traffic mixes
- Error-injection tests that check how the design recovers
- A functional coverage model mapped to the specification
- Regression lists ready to run in Lumina
Test focus for this protocol family
- Each timing parameter at its minimum
- Initialisation and training sequences
- Refresh and power-down under traffic
- ECC, CRC and parity errors
What you receive.
- Readable source of every component
- The test suite and its coverage model
- An example environment connected to a sample design
- User guide, integration guide and release notes
- Scripts to run the examples in Lumina
Where it is used.
- Server and PC memory controllers
- AI and networking SoCs
- DDR PHY and controller IP
Frequently asked questions.
What is Lumina VIP for DDR5?
Lumina VIP for DDR5 is a set of verification products for designs that use DDR5: assertion IP, memory model and synthesizable transactor. DDR5 SDRAM device model with two sub-channels per DIMM channel, command and data training, refresh management, on-die ECC and every timing check.
Which DDR5 versions does it support?
JESD79-5 · x4, x8, x16 · 3DS, as published by JEDEC. If you need another version or option, tell us which one.
Which verification components are included?
Memory device model and Passive monitor and timing checker. Each one can be used on its own or together with the others in one environment.
What language and methodology does it use?
The verification IP and models are written in SystemVerilog with UVM, as readable source your team can extend. The assertion IP uses SystemVerilog Assertions, with bind files for attaching to your design. The transactors are synthesizable RTL for FPGA prototyping and hardware-assisted verification.
How does it work with Lumina?
It runs in Lumina Sim beside your RTL, and the assertion IP proves your design in Lumina Formal. Protocol coverage merges into the same database as your own coverage, and every violation names the rule it broke and the transaction that broke it.
Which tests come with it?
Directed tests for each feature of the specification. Constrained-random tests across configurations and traffic mixes. Error-injection tests that check how the design recovers. A functional coverage model mapped to the specification. Regression lists ready to run in Lumina. For this protocol family the tests focus on: each timing parameter at its minimum, initialisation and training sequences, refresh and power-down under traffic and ECC, CRC and parity errors.
What is delivered?
Readable source of every component. The test suite and its coverage model. An example environment connected to a sample design. User guide, integration guide and release notes. Scripts to run the examples in Lumina.
How can I get Lumina VIP for DDR5?
Lumina VIP for DDR5 is in preview. Email hello@lumeeslab.com with the versions and product types you need.
Need VIP for a protocol?
Tell us which protocols and versions you need. We also add protocols on request.
Lumina VIP
hello@lumeeslab.comHelpful to include
- The protocols and versions
- Product types: VIP, assertion IP, memory model, transactor
- Your schedule