DDR6 Memory Model
Device model for the next DDR generation, tracking the draft standard: sub-channels, commands, training and timing checks.
DDR6 memory model
DDR6 is the next main-memory generation being defined at JEDEC. Our model follows the draft so controller teams can start early and track changes as the standard settles.
Lumina VIP for DDR6 covers DDR6 (draft), as published by JEDEC. It comes as memory model, built for Lumina, so the same components run in simulation and report their results in one place.
What the DDR6 VIP covers.
Device model
- Sub-channel architecture and command encoding of the draft
- Training modes and mode registers as defined so far
- Timing checks updated with each draft
Checks and error injection
- Configurable timing tables so draft values can be updated
- Refresh, self-refresh and power-down rules
- On-die ECC and error injection
What it checks
- Command sequences against every timing parameter
- Initialisation, training and mode-register settings
- Refresh, self-refresh and power-down rules
- Data integrity, ECC and CRC
Memory model capabilities
- Part configurations selected by density, width and speed grade
- Every timing parameter checked, with the violated parameter named in the message
- Sparse storage, so large densities use little host memory
- Backdoor preload, peek, poke and dump of the contents
- Mode registers and power states modelled
- Configurable error injection on read data
Why Lumina VIP.
- Fast DDR6 testbench bring-up: connect the agents, pick a test and run
- Every failure names the rule it broke and the transaction that broke it
- Protocol coverage merges with your design coverage in one database
- Readable SystemVerilog and UVM source your team can extend
- Runs natively in Lumina Sim, with no wrappers and no separate compile
- Results structured for engineers and AI agents alike
Verification components.
Each component works on its own or together with the others in one environment, in active or passive mode.
- 01Memory device model
- 02Passive monitor and timing checker
DDR6 products.
DDR6 memory model
Device models that behave like the memory part: commands, modes, refresh and every timing parameter checked.
Includes
- Configurable density, width, speed grade and timing
- Timing and protocol checks on every command
- Mode registers, training and power-down behaviour
- Backdoor access to preload and inspect memory contents
Test suite and coverage.
- Directed tests for each feature of the specification
- Constrained-random tests across configurations and traffic mixes
- Error-injection tests that check how the design recovers
- A functional coverage model mapped to the specification
- Regression lists ready to run in Lumina
Test focus for this protocol family
- Each timing parameter at its minimum
- Initialisation and training sequences
- Refresh and power-down under traffic
- ECC, CRC and parity errors
What you receive.
- Readable source of every component
- The test suite and its coverage model
- An example environment connected to a sample design
- User guide, integration guide and release notes
- Scripts to run the examples in Lumina
Where it is used.
- Memory controllers and PHYs
- AI accelerators and GPUs
- Mobile, automotive and server SoCs
Frequently asked questions.
What is Lumina VIP for DDR6?
Lumina VIP for DDR6 is a set of verification products for designs that use DDR6: memory model. Device model for the next DDR generation, tracking the draft standard: sub-channels, commands, training and timing checks.
Which DDR6 versions does it support?
DDR6 (draft), as published by JEDEC. If you need another version or option, tell us which one.
Which verification components are included?
Memory device model and Passive monitor and timing checker. Each one can be used on its own or together with the others in one environment.
What language and methodology does it use?
The verification IP and models are written in SystemVerilog with UVM, as readable source your team can extend.
How does it work with Lumina?
It runs in Lumina Sim beside your RTL. Protocol coverage merges into the same database as your own coverage, and every violation names the rule it broke and the transaction that broke it.
Which tests come with it?
Directed tests for each feature of the specification. Constrained-random tests across configurations and traffic mixes. Error-injection tests that check how the design recovers. A functional coverage model mapped to the specification. Regression lists ready to run in Lumina. For this protocol family the tests focus on: each timing parameter at its minimum, initialisation and training sequences, refresh and power-down under traffic and ECC, CRC and parity errors.
What is delivered?
Readable source of every component. The test suite and its coverage model. An example environment connected to a sample design. User guide, integration guide and release notes. Scripts to run the examples in Lumina.
How can I get Lumina VIP for DDR6?
Lumina VIP for DDR6 is in preview. Email hello@lumeeslab.com with the versions and product types you need.
Need VIP for a protocol?
Tell us which protocols and versions you need. We also add protocols on request.
Lumina VIP
hello@lumeeslab.comHelpful to include
- The protocols and versions
- Product types: VIP, assertion IP, memory model, transactor
- Your schedule