GPIO and SGPIO Verification IP
General-purpose I/O drivers and monitors, and the serial GPIO bus used for storage enclosure indicators.
GPIO and SGPIO verification IP
GPIO models drive and sample general-purpose pins with configurable direction, edges and timing.
Lumina VIP for GPIO and SGPIO covers GPIO · SGPIO (SFF-8485), as published by Industry · SFF-8485. It comes as verification IP, built for Lumina, so the same components run in simulation and report their results in one place.
What the GPIO and SGPIO VIP covers.
Features
- Input, output and open-drain pins
- Edge and level interrupts
- Debounce and pulse-width checks
Checks and error injection
- Random and scheduled pin changes
- Interrupt latency measured from pin edge to event
- Glitches injected on inputs
What it checks
- Bit and byte timing in every speed mode
- Addressing, commands and responses
- Multi-controller arbitration where defined
- Error and timeout conditions
Verification IP capabilities
- Active and passive agents for every protocol role, set per instance
- Bus widths, timing and optional features set by parameters, and changeable while a test runs
- A sequence library from basic directed traffic to constrained-random stress
- Error injection, static or on the fly, with checks that the expected error was seen
- Protocol checks that run in real time, each tied to a rule of the specification
- Scoreboards that check data end to end
- Throughput, latency and utilisation statistics for each interface
- Callbacks at each stage for your own checks and stimulus
- UVM register model adapters for protocols that carry register access
- Transaction logs and messages linked to the waveform for debug
Why Lumina VIP.
- Fast GPIO and SGPIO testbench bring-up: connect the agents, pick a test and run
- Every failure names the rule it broke and the transaction that broke it
- Protocol coverage merges with your design coverage in one database
- Readable SystemVerilog and UVM source your team can extend
- Runs natively in Lumina Sim, with no wrappers and no separate compile
- Results structured for engineers and AI agents alike
Verification components.
Each component works on its own or together with the others in one environment, in active or passive mode.
- 01Pin driver
- 02Pin monitor
GPIO and SGPIO products.
GPIO and SGPIO verification IP
UVM agents that drive and check a protocol in simulation, in every role the protocol defines.
Includes
- Active and passive UVM agents for each protocol role
- Configurable sequences, from directed to constrained-random
- Protocol checks that flag violations with a spec reference
- Functional coverage of the protocol's features
- Scoreboards and transaction logs readable by people and AI agents
Test suite and coverage.
- Directed tests for each feature of the specification
- Constrained-random tests across configurations and traffic mixes
- Error-injection tests that check how the design recovers
- A functional coverage model mapped to the specification
- Regression lists ready to run in Lumina
Test focus for this protocol family
- Every mode and speed in scope
- Multi-device topologies
- Timing at the edges of the specification
- Protocol and line errors
What you receive.
- Readable source of every component
- The test suite and its coverage model
- An example environment connected to a sample design
- User guide, integration guide and release notes
- Scripts to run the examples in Lumina
Where it is used.
- Microcontrollers and embedded SoCs
- Sensors, power management and board control
- Debug and test access
Frequently asked questions.
What is Lumina VIP for GPIO and SGPIO?
Lumina VIP for GPIO and SGPIO is a set of verification products for designs that use GPIO and SGPIO: verification IP. General-purpose I/O drivers and monitors, and the serial GPIO bus used for storage enclosure indicators.
Which GPIO and SGPIO versions does it support?
GPIO · SGPIO (SFF-8485), as published by Industry · SFF-8485. If you need another version or option, tell us which one.
Which verification components are included?
Pin driver and Pin monitor. Each one can be used on its own or together with the others in one environment.
What language and methodology does it use?
The verification IP and models are written in SystemVerilog with UVM, as readable source your team can extend.
How does it work with Lumina?
It runs in Lumina Sim beside your RTL. Protocol coverage merges into the same database as your own coverage, and every violation names the rule it broke and the transaction that broke it.
Which tests come with it?
Directed tests for each feature of the specification. Constrained-random tests across configurations and traffic mixes. Error-injection tests that check how the design recovers. A functional coverage model mapped to the specification. Regression lists ready to run in Lumina. For this protocol family the tests focus on: every mode and speed in scope, multi-device topologies, timing at the edges of the specification and protocol and line errors.
What is delivered?
Readable source of every component. The test suite and its coverage model. An example environment connected to a sample design. User guide, integration guide and release notes. Scripts to run the examples in Lumina.
How can I get Lumina VIP for GPIO and SGPIO?
Lumina VIP for GPIO and SGPIO is in preview. Email hello@lumeeslab.com with the versions and product types you need.
Need VIP for a protocol?
Tell us which protocols and versions you need. We also add protocols on request.
Lumina VIP
hello@lumeeslab.comHelpful to include
- The protocols and versions
- Product types: VIP, assertion IP, memory model, transactor
- Your schedule