I2C Verification IP
Controllers and targets: 7- and 10-bit addressing, clock stretching, arbitration between controllers, repeated starts and every speed mode.
I2C verification IP
I2C is the two-wire bus that connects sensors, EEPROMs, power controllers and configuration registers on almost every board and SoC.
Lumina VIP for I2C covers Standard · Fast · Fast-mode Plus · High-speed · Ultra Fast, as published by NXP. It comes as verification IP, assertion IP and synthesizable transactor, built for Lumina, so the same components run in simulation and formal proofs and report their results in one place.
What the I2C VIP covers.
Protocol
- Start, repeated start, stop, addressing and ACK and NACK
- Clock stretching and multi-controller arbitration
- 7-bit and 10-bit addressing, general call and device ID
- Standard, Fast, Fast-mode Plus, High-speed and Ultra-fast modes
Errors and timing
- Setup, hold and spike-filter timing checked
- NACKs, lost arbitration and bus hangs injected
What it checks
- Bit and byte timing in every speed mode
- Addressing, commands and responses
- Multi-controller arbitration where defined
- Error and timeout conditions
Verification IP capabilities
- Active and passive agents for every protocol role, set per instance
- Bus widths, timing and optional features set by parameters, and changeable while a test runs
- A sequence library from basic directed traffic to constrained-random stress
- Error injection, static or on the fly, with checks that the expected error was seen
- Protocol checks that run in real time, each tied to a rule of the specification
- Scoreboards that check data end to end
- Throughput, latency and utilisation statistics for each interface
- Callbacks at each stage for your own checks and stimulus
- UVM register model adapters for protocols that carry register access
- Transaction logs and messages linked to the waveform for debug
Assertion IP capabilities
- One assertion per protocol rule, named after the rule
- Assumptions that constrain inputs in formal and become checks in simulation
- Cover properties for each protocol scenario
- Parameters for widths and optional features
- The same properties run in formal proofs and in simulation
- Bind files that attach to your RTL without edits
Transactor capabilities
- Synthesizable RTL for FPGA prototypes and emulators
- A transaction-level interface, so tests move unchanged from simulation
- Protocol checkers and monitors that run at hardware speed
- Streaming and buffered modes for throughput
Why Lumina VIP.
- Fast I2C testbench bring-up: connect the agents, pick a test and run
- Every failure names the rule it broke and the transaction that broke it
- Protocol coverage merges with your design coverage in one database
- Readable SystemVerilog and UVM source your team can extend
- The same scenarios run in simulation, on FPGA and on silicon
- Assertion IP proves the protocol rules in Lumina Formal
- Runs natively in Lumina Sim, with no wrappers and no separate compile
- Results structured for engineers and AI agents alike
Verification components.
Each component works on its own or together with the others in one environment, in active or passive mode.
- 01Controller
- 02Target
- 03Passive monitor
I2C products.
I2C verification IP
UVM agents that drive and check a protocol in simulation, in every role the protocol defines.
Includes
- Active and passive UVM agents for each protocol role
- Configurable sequences, from directed to constrained-random
- Protocol checks that flag violations with a spec reference
- Functional coverage of the protocol's features
- Scoreboards and transaction logs readable by people and AI agents
I2C assertion IP
SystemVerilog assertions, assumptions and cover properties that prove a design follows the protocol in Lumina Formal, or check it in simulation.
Includes
- Assertions for every protocol rule, each named after its rule
- Assumptions to constrain the inputs in formal proofs
- Cover properties for the protocol's scenarios
- Bind files for attaching to your design without edits
I2C synthesizable transactor
Synthesizable models of the protocol for FPGA prototyping and hardware-assisted verification, driven from the same tests as the VIP.
Includes
- Synthesizable RTL for the protocol's roles
- A transaction interface to software or a testbench
- Monitors and checkers that run at hardware speed
Test suite and coverage.
- Directed tests for each feature of the specification
- Constrained-random tests across configurations and traffic mixes
- Error-injection tests that check how the design recovers
- A functional coverage model mapped to the specification
- Regression lists ready to run in Lumina
Test focus for this protocol family
- Every mode and speed in scope
- Multi-device topologies
- Timing at the edges of the specification
- Protocol and line errors
What you receive.
- Readable source of every component
- The test suite and its coverage model
- An example environment connected to a sample design
- User guide, integration guide and release notes
- Scripts to run the examples in Lumina
Where it is used.
- Microcontrollers and embedded SoCs
- Sensors, power management and board control
- Debug and test access
Frequently asked questions.
What is Lumina VIP for I2C?
Lumina VIP for I2C is a set of verification products for designs that use I2C: verification IP, assertion IP and synthesizable transactor. Controllers and targets: 7- and 10-bit addressing, clock stretching, arbitration between controllers, repeated starts and every speed mode.
Which I2C versions does it support?
Standard · Fast · Fast-mode Plus · High-speed · Ultra Fast, as published by NXP. If you need another version or option, tell us which one.
Which verification components are included?
Controller, Target and Passive monitor. Each one can be used on its own or together with the others in one environment.
What language and methodology does it use?
The verification IP and models are written in SystemVerilog with UVM, as readable source your team can extend. The assertion IP uses SystemVerilog Assertions, with bind files for attaching to your design. The transactors are synthesizable RTL for FPGA prototyping and hardware-assisted verification.
How does it work with Lumina?
It runs in Lumina Sim beside your RTL, and the assertion IP proves your design in Lumina Formal. Protocol coverage merges into the same database as your own coverage, and every violation names the rule it broke and the transaction that broke it.
Which tests come with it?
Directed tests for each feature of the specification. Constrained-random tests across configurations and traffic mixes. Error-injection tests that check how the design recovers. A functional coverage model mapped to the specification. Regression lists ready to run in Lumina. For this protocol family the tests focus on: every mode and speed in scope, multi-device topologies, timing at the edges of the specification and protocol and line errors.
What is delivered?
Readable source of every component. The test suite and its coverage model. An example environment connected to a sample design. User guide, integration guide and release notes. Scripts to run the examples in Lumina.
How can I get Lumina VIP for I2C?
Lumina VIP for I2C is in preview. Email hello@lumeeslab.com with the versions and product types you need.
Need VIP for a protocol?
Tell us which protocols and versions you need. We also add protocols on request.
Lumina VIP
hello@lumeeslab.comHelpful to include
- The protocols and versions
- Product types: VIP, assertion IP, memory model, transactor
- Your schedule