MIPI I3C Verification IP
Controllers and targets with dynamic addressing, in-band interrupts, HDR modes, hot-join and mixed buses with legacy I2C devices.
MIPI I3C verification IP
MIPI I3C is the successor to I2C for sensors and control, with higher rates, in-band interrupts and dynamic addressing, while still working with I2C devices.
Lumina VIP for MIPI I3C covers I3C 1.1.1 · 1.2 · I3C Basic, as published by MIPI Alliance. It comes as verification IP, synthesizable transactor and post-silicon validation IP, built for Lumina, so the same components run in simulation and report their results in one place.
What the MIPI I3C VIP covers.
Protocol
- SDR mode and HDR-DDR, HDR-TSP and HDR-BT modes
- Dynamic address assignment and common command codes
- In-band interrupts, hot-join and secondary controller hand-off
- Mixed buses with legacy I2C targets
Scenarios and options
- Target reset actions and dynamic address changes
- Parity, CRC and protocol errors injected
What it checks
- Packet structure, ECC and CRC
- PHY states, lane control and timing
- Virtual channels, data types and commands
- Low-power entry and exit
Verification IP capabilities
- Active and passive agents for every protocol role, set per instance
- Bus widths, timing and optional features set by parameters, and changeable while a test runs
- A sequence library from basic directed traffic to constrained-random stress
- Error injection, static or on the fly, with checks that the expected error was seen
- Protocol checks that run in real time, each tied to a rule of the specification
- Scoreboards that check data end to end
- Throughput, latency and utilisation statistics for each interface
- Callbacks at each stage for your own checks and stimulus
- UVM register model adapters for protocols that carry register access
- Transaction logs and messages linked to the waveform for debug
Transactor capabilities
- Synthesizable RTL for FPGA prototypes and emulators
- A transaction-level interface, so tests move unchanged from simulation
- Protocol checkers and monitors that run at hardware speed
- Streaming and buffered modes for throughput
Post-silicon validation capabilities
- Acts as controller, target or monitor on the board
- Reuses the scenarios written before tape-out
- Captures bus traffic with timestamps
- Injects errors on the live bus
Why Lumina VIP.
- Fast MIPI I3C testbench bring-up: connect the agents, pick a test and run
- Every failure names the rule it broke and the transaction that broke it
- Protocol coverage merges with your design coverage in one database
- Readable SystemVerilog and UVM source your team can extend
- The same scenarios run in simulation, on FPGA and on silicon
- Runs natively in Lumina Sim, with no wrappers and no separate compile
- Results structured for engineers and AI agents alike
Verification components.
Each component works on its own or together with the others in one environment, in active or passive mode.
- 01Controller
- 02Target
- 03Passive monitor
MIPI I3C products.
MIPI I3C verification IP
UVM agents that drive and check a protocol in simulation, in every role the protocol defines.
Includes
- Active and passive UVM agents for each protocol role
- Configurable sequences, from directed to constrained-random
- Protocol checks that flag violations with a spec reference
- Functional coverage of the protocol's features
- Scoreboards and transaction logs readable by people and AI agents
MIPI I3C synthesizable transactor
Synthesizable models of the protocol for FPGA prototyping and hardware-assisted verification, driven from the same tests as the VIP.
Includes
- Synthesizable RTL for the protocol's roles
- A transaction interface to software or a testbench
- Monitors and checkers that run at hardware speed
MIPI I3C post-silicon validation IP
Drives and checks the bus on a real board through an FPGA, to validate silicon with the scenarios used before tape-out.
Includes
- FPGA images that act as controller, target or monitor
- Scenario reuse from pre-silicon tests
- Logs of the bus traffic from the board
Test suite and coverage.
- Directed tests for each feature of the specification
- Constrained-random tests across configurations and traffic mixes
- Error-injection tests that check how the design recovers
- A functional coverage model mapped to the specification
- Regression lists ready to run in Lumina
Test focus for this protocol family
- Every lane count and data rate in scope
- Low-power and high-speed transitions
- Each packet and data type
- Header, CRC and protocol errors
What you receive.
- Readable source of every component
- The test suite and its coverage model
- An example environment connected to a sample design
- User guide, integration guide and release notes
- Scripts to run the examples in Lumina
Where it is used.
- Phones and wearables
- Automotive cameras and displays
- IoT and imaging devices
Frequently asked questions.
What is Lumina VIP for MIPI I3C?
Lumina VIP for MIPI I3C is a set of verification products for designs that use MIPI I3C: verification IP, synthesizable transactor and post-silicon validation IP. Controllers and targets with dynamic addressing, in-band interrupts, HDR modes, hot-join and mixed buses with legacy I2C devices.
Which MIPI I3C versions does it support?
I3C 1.1.1 · 1.2 · I3C Basic, as published by MIPI Alliance. If you need another version or option, tell us which one.
Which verification components are included?
Controller, Target and Passive monitor. Each one can be used on its own or together with the others in one environment.
What language and methodology does it use?
The verification IP and models are written in SystemVerilog with UVM, as readable source your team can extend. The transactors are synthesizable RTL for FPGA prototyping and hardware-assisted verification. The post-silicon validation IP runs on an FPGA connected to your board.
How does it work with Lumina?
It runs in Lumina Sim beside your RTL. Protocol coverage merges into the same database as your own coverage, and every violation names the rule it broke and the transaction that broke it.
Which tests come with it?
Directed tests for each feature of the specification. Constrained-random tests across configurations and traffic mixes. Error-injection tests that check how the design recovers. A functional coverage model mapped to the specification. Regression lists ready to run in Lumina. For this protocol family the tests focus on: every lane count and data rate in scope, low-power and high-speed transitions, each packet and data type and header, CRC and protocol errors.
What is delivered?
Readable source of every component. The test suite and its coverage model. An example environment connected to a sample design. User guide, integration guide and release notes. Scripts to run the examples in Lumina.
How can I get Lumina VIP for MIPI I3C?
Lumina VIP for MIPI I3C is in preview. Email hello@lumeeslab.com with the versions and product types you need.
Need VIP for a protocol?
Tell us which protocols and versions you need. We also add protocols on request.
Lumina VIP
hello@lumeeslab.comHelpful to include
- The protocols and versions
- Product types: VIP, assertion IP, memory model, transactor
- Your schedule