PCI Express Verification IP
Root complex and endpoint models across the transaction, data link and physical layers, from 2.5 GT/s to 128 GT/s, including flit mode, FEC and L0p.
PCI Express verification IP
PCI Express is the main high-speed I/O link of computers, servers and accelerators. Each generation has doubled the transfer rate, from 2.5 GT/s in Gen1 to 64 GT/s with PAM4 and flit mode in Gen6 and 128 GT/s in Gen7, while keeping software compatibility.
Lumina VIP for PCI Express covers Gen1 to Gen7 · Flit mode · PAM4, as published by PCI-SIG. It comes as verification IP and synthesizable transactor, built for Lumina, so the same components run in simulation and report their results in one place.
What the PCI Express VIP covers.
Transaction layer
- Memory, I/O, configuration and message requests and completions
- Ordering rules, relaxed ordering and ID-based ordering
- Flow control credits per type, ECRC and poisoned TLPs
- Atomic operations, TLP prefixes, 10-bit tags and TLP processing hints
Data link layer
- ACK and NAK protocol, sequence numbers and replay buffer
- DLLPs for flow control and power management
- Flit mode with FEC and CRC from Gen6
Physical layer
- LTSSM with every state and transition, including recovery and loopback
- 8b/10b, 128b/130b and 1b/1b encoding; lane reversal and polarity inversion
- Equalization phases, speed and width changes, L0s, L1, L1 substates and L0p
- Serial and PIPE interfaces to the PHY
Configuration and errors
- Configuration space and capability structures checked against the design
- Advanced error reporting, downstream port containment
- Error injection at every layer
What it checks
- Link training and the state machines of every layer
- Transaction ordering, flow control credits and replay
- Configuration space, capabilities and error reporting
- Power states and speed and width changes
Verification IP capabilities
- Active and passive agents for every protocol role, set per instance
- Bus widths, timing and optional features set by parameters, and changeable while a test runs
- A sequence library from basic directed traffic to constrained-random stress
- Error injection, static or on the fly, with checks that the expected error was seen
- Protocol checks that run in real time, each tied to a rule of the specification
- Scoreboards that check data end to end
- Throughput, latency and utilisation statistics for each interface
- Callbacks at each stage for your own checks and stimulus
- UVM register model adapters for protocols that carry register access
- Transaction logs and messages linked to the waveform for debug
Transactor capabilities
- Synthesizable RTL for FPGA prototypes and emulators
- A transaction-level interface, so tests move unchanged from simulation
- Protocol checkers and monitors that run at hardware speed
- Streaming and buffered modes for throughput
Why Lumina VIP.
- Fast PCI Express testbench bring-up: connect the agents, pick a test and run
- Every failure names the rule it broke and the transaction that broke it
- Protocol coverage merges with your design coverage in one database
- Readable SystemVerilog and UVM source your team can extend
- The same scenarios run in simulation, on FPGA and on silicon
- Runs natively in Lumina Sim, with no wrappers and no separate compile
- Results structured for engineers and AI agents alike
Verification components.
Each component works on its own or together with the others in one environment, in active or passive mode.
- 01Root complex
- 02Endpoint
- 03Switch port
- 04Passive monitor and protocol analyser
PCI Express products.
PCI Express verification IP
UVM agents that drive and check a protocol in simulation, in every role the protocol defines.
Includes
- Active and passive UVM agents for each protocol role
- Configurable sequences, from directed to constrained-random
- Protocol checks that flag violations with a spec reference
- Functional coverage of the protocol's features
- Scoreboards and transaction logs readable by people and AI agents
PCI Express synthesizable transactor
Synthesizable models of the protocol for FPGA prototyping and hardware-assisted verification, driven from the same tests as the VIP.
Includes
- Synthesizable RTL for the protocol's roles
- A transaction interface to software or a testbench
- Monitors and checkers that run at hardware speed
Test suite and coverage.
- Directed tests for each feature of the specification
- Constrained-random tests across configurations and traffic mixes
- Error-injection tests that check how the design recovers
- A functional coverage model mapped to the specification
- Regression lists ready to run in Lumina
Test focus for this protocol family
- Link training at every rate and width
- Flow-control credit exhaustion and replay
- Malformed TLPs, LCRC and ECRC errors
- Power-state entry and exit under traffic
What you receive.
- Readable source of every component
- The test suite and its coverage model
- An example environment connected to a sample design
- User guide, integration guide and release notes
- Scripts to run the examples in Lumina
Where it is used.
- Servers and data-centre accelerators
- SSD controllers
- GPUs and AI accelerators
- Network and storage adapters
Frequently asked questions.
What is Lumina VIP for PCI Express?
Lumina VIP for PCI Express is a set of verification products for designs that use PCI Express: verification IP and synthesizable transactor. Root complex and endpoint models across the transaction, data link and physical layers, from 2.5 GT/s to 128 GT/s, including flit mode, FEC and L0p.
Which PCI Express versions does it support?
Gen1 to Gen7 · Flit mode · PAM4, as published by PCI-SIG. If you need another version or option, tell us which one.
Which verification components are included?
Root complex, Endpoint, Switch port and Passive monitor and protocol analyser. Each one can be used on its own or together with the others in one environment.
What language and methodology does it use?
The verification IP and models are written in SystemVerilog with UVM, as readable source your team can extend. The transactors are synthesizable RTL for FPGA prototyping and hardware-assisted verification.
How does it work with Lumina?
It runs in Lumina Sim beside your RTL. Protocol coverage merges into the same database as your own coverage, and every violation names the rule it broke and the transaction that broke it.
Which tests come with it?
Directed tests for each feature of the specification. Constrained-random tests across configurations and traffic mixes. Error-injection tests that check how the design recovers. A functional coverage model mapped to the specification. Regression lists ready to run in Lumina. For this protocol family the tests focus on: link training at every rate and width, flow-control credit exhaustion and replay, malformed TLPs, LCRC and ECRC errors and power-state entry and exit under traffic.
What is delivered?
Readable source of every component. The test suite and its coverage model. An example environment connected to a sample design. User guide, integration guide and release notes. Scripts to run the examples in Lumina.
How can I get Lumina VIP for PCI Express?
Lumina VIP for PCI Express is in preview. Email hello@lumeeslab.com with the versions and product types you need.
Need VIP for a protocol?
Tell us which protocols and versions you need. We also add protocols on request.
Lumina VIP
hello@lumeeslab.comHelpful to include
- The protocols and versions
- Product types: VIP, assertion IP, memory model, transactor
- Your schedule