UCIe Verification IP
Die-to-die links for chiplets: the protocol, adapter and physical layers, standard and advanced packages, link training, sideband and retimers.
UCIe verification IP
UCIe is the open standard for connecting chiplets inside a package. It defines a physical layer for standard and advanced packages, a die-to-die adapter, and the mapping of PCIe, CXL and streaming protocols onto the link.
Lumina VIP for UCIe covers UCIe 1.1 · 2.0 · 3.0 · retimer, as published by UCIe Consortium. It comes as verification IP, built for Lumina, so the same components run in simulation and report their results in one place.
What the UCIe VIP covers.
Physical layer
- Standard and advanced package modules, lane counts and data rates
- Link training, lane repair and width degradation
- Sideband messages and register access
Die-to-die adapter and protocols
- Flit formats, CRC and retry
- PCIe, CXL and streaming protocol mapping
- Raw mode and the FDI and RDI interfaces
- Retimers for off-package links
What it checks
- Link training and the state machines of every layer
- Transaction ordering, flow control credits and replay
- Configuration space, capabilities and error reporting
- Power states and speed and width changes
Verification IP capabilities
- Active and passive agents for every protocol role, set per instance
- Bus widths, timing and optional features set by parameters, and changeable while a test runs
- A sequence library from basic directed traffic to constrained-random stress
- Error injection, static or on the fly, with checks that the expected error was seen
- Protocol checks that run in real time, each tied to a rule of the specification
- Scoreboards that check data end to end
- Throughput, latency and utilisation statistics for each interface
- Callbacks at each stage for your own checks and stimulus
- UVM register model adapters for protocols that carry register access
- Transaction logs and messages linked to the waveform for debug
Why Lumina VIP.
- Fast UCIe testbench bring-up: connect the agents, pick a test and run
- Every failure names the rule it broke and the transaction that broke it
- Protocol coverage merges with your design coverage in one database
- Readable SystemVerilog and UVM source your team can extend
- Runs natively in Lumina Sim, with no wrappers and no separate compile
- Results structured for engineers and AI agents alike
Verification components.
Each component works on its own or together with the others in one environment, in active or passive mode.
- 01Die model (protocol, adapter, PHY)
- 02FDI and RDI agents
- 03Retimer model
- 04Passive monitor
UCIe products.
UCIe verification IP
UVM agents that drive and check a protocol in simulation, in every role the protocol defines.
Includes
- Active and passive UVM agents for each protocol role
- Configurable sequences, from directed to constrained-random
- Protocol checks that flag violations with a spec reference
- Functional coverage of the protocol's features
- Scoreboards and transaction logs readable by people and AI agents
Test suite and coverage.
- Directed tests for each feature of the specification
- Constrained-random tests across configurations and traffic mixes
- Error-injection tests that check how the design recovers
- A functional coverage model mapped to the specification
- Regression lists ready to run in Lumina
Test focus for this protocol family
- Link training at every rate and width
- Flow-control credit exhaustion and replay
- Malformed TLPs, LCRC and ECRC errors
- Power-state entry and exit under traffic
What you receive.
- Readable source of every component
- The test suite and its coverage model
- An example environment connected to a sample design
- User guide, integration guide and release notes
- Scripts to run the examples in Lumina
Where it is used.
- Chiplet-based processors and accelerators
- I/O and memory chiplets
Frequently asked questions.
What is Lumina VIP for UCIe?
Lumina VIP for UCIe is a set of verification products for designs that use UCIe: verification IP. Die-to-die links for chiplets: the protocol, adapter and physical layers, standard and advanced packages, link training, sideband and retimers.
Which UCIe versions does it support?
UCIe 1.1 · 2.0 · 3.0 · retimer, as published by UCIe Consortium. If you need another version or option, tell us which one.
Which verification components are included?
Die model (protocol, adapter, PHY), FDI and RDI agents, Retimer model and Passive monitor. Each one can be used on its own or together with the others in one environment.
What language and methodology does it use?
The verification IP and models are written in SystemVerilog with UVM, as readable source your team can extend.
How does it work with Lumina?
It runs in Lumina Sim beside your RTL. Protocol coverage merges into the same database as your own coverage, and every violation names the rule it broke and the transaction that broke it.
Which tests come with it?
Directed tests for each feature of the specification. Constrained-random tests across configurations and traffic mixes. Error-injection tests that check how the design recovers. A functional coverage model mapped to the specification. Regression lists ready to run in Lumina. For this protocol family the tests focus on: link training at every rate and width, flow-control credit exhaustion and replay, malformed TLPs, LCRC and ECRC errors and power-state entry and exit under traffic.
What is delivered?
Readable source of every component. The test suite and its coverage model. An example environment connected to a sample design. User guide, integration guide and release notes. Scripts to run the examples in Lumina.
How can I get Lumina VIP for UCIe?
Lumina VIP for UCIe is in preview. Email hello@lumeeslab.com with the versions and product types you need.
Need VIP for a protocol?
Tell us which protocols and versions you need. We also add protocols on request.
Lumina VIP
hello@lumeeslab.comHelpful to include
- The protocols and versions
- Product types: VIP, assertion IP, memory model, transactor
- Your schedule