UALink Verification IP
The open scale-up interconnect between AI accelerators: transaction, data link and physical layers, memory semantics and switch traffic.
UALink verification IP
UALink is an open interconnect for scaling up AI systems: it connects hundreds of accelerators with memory semantics, so one accelerator can read and write another's memory directly through switches.
Lumina VIP for UALink covers UALink 1.0, as published by UALink Consortium. It comes as verification IP, built for Lumina, so the same components run in simulation and report their results in one place.
What the UALink VIP covers.
Protocol
- Transaction layer: reads, writes and atomics with memory semantics
- Data link layer: flits, CRC and link-level retry
- Physical layer based on Ethernet SerDes
- Switch traffic between many accelerators
Scenarios and options
- Pods of accelerators connected through switches
- CRC errors with link-level retry under load
What it checks
- Link training and the state machines of every layer
- Transaction ordering, flow control credits and replay
- Configuration space, capabilities and error reporting
- Power states and speed and width changes
Verification IP capabilities
- Active and passive agents for every protocol role, set per instance
- Bus widths, timing and optional features set by parameters, and changeable while a test runs
- A sequence library from basic directed traffic to constrained-random stress
- Error injection, static or on the fly, with checks that the expected error was seen
- Protocol checks that run in real time, each tied to a rule of the specification
- Scoreboards that check data end to end
- Throughput, latency and utilisation statistics for each interface
- Callbacks at each stage for your own checks and stimulus
- UVM register model adapters for protocols that carry register access
- Transaction logs and messages linked to the waveform for debug
Why Lumina VIP.
- Fast UALink testbench bring-up: connect the agents, pick a test and run
- Every failure names the rule it broke and the transaction that broke it
- Protocol coverage merges with your design coverage in one database
- Readable SystemVerilog and UVM source your team can extend
- Runs natively in Lumina Sim, with no wrappers and no separate compile
- Results structured for engineers and AI agents alike
Verification components.
Each component works on its own or together with the others in one environment, in active or passive mode.
- 01Accelerator endpoint
- 02Switch port
- 03Passive monitor
UALink products.
UALink verification IP
UVM agents that drive and check a protocol in simulation, in every role the protocol defines.
Includes
- Active and passive UVM agents for each protocol role
- Configurable sequences, from directed to constrained-random
- Protocol checks that flag violations with a spec reference
- Functional coverage of the protocol's features
- Scoreboards and transaction logs readable by people and AI agents
Test suite and coverage.
- Directed tests for each feature of the specification
- Constrained-random tests across configurations and traffic mixes
- Error-injection tests that check how the design recovers
- A functional coverage model mapped to the specification
- Regression lists ready to run in Lumina
Test focus for this protocol family
- Link training at every rate and width
- Flow-control credit exhaustion and replay
- Malformed TLPs, LCRC and ECRC errors
- Power-state entry and exit under traffic
What you receive.
- Readable source of every component
- The test suite and its coverage model
- An example environment connected to a sample design
- User guide, integration guide and release notes
- Scripts to run the examples in Lumina
Where it is used.
- Data-centre accelerators and SmartNICs
- SSD and storage controllers
- Chiplets and multi-die packages
Frequently asked questions.
What is Lumina VIP for UALink?
Lumina VIP for UALink is a set of verification products for designs that use UALink: verification IP. The open scale-up interconnect between AI accelerators: transaction, data link and physical layers, memory semantics and switch traffic.
Which UALink versions does it support?
UALink 1.0, as published by UALink Consortium. If you need another version or option, tell us which one.
Which verification components are included?
Accelerator endpoint, Switch port and Passive monitor. Each one can be used on its own or together with the others in one environment.
What language and methodology does it use?
The verification IP and models are written in SystemVerilog with UVM, as readable source your team can extend.
How does it work with Lumina?
It runs in Lumina Sim beside your RTL. Protocol coverage merges into the same database as your own coverage, and every violation names the rule it broke and the transaction that broke it.
Which tests come with it?
Directed tests for each feature of the specification. Constrained-random tests across configurations and traffic mixes. Error-injection tests that check how the design recovers. A functional coverage model mapped to the specification. Regression lists ready to run in Lumina. For this protocol family the tests focus on: link training at every rate and width, flow-control credit exhaustion and replay, malformed TLPs, LCRC and ECRC errors and power-state entry and exit under traffic.
What is delivered?
Readable source of every component. The test suite and its coverage model. An example environment connected to a sample design. User guide, integration guide and release notes. Scripts to run the examples in Lumina.
How can I get Lumina VIP for UALink?
Lumina VIP for UALink is in preview. Email hello@lumeeslab.com with the versions and product types you need.
Need VIP for a protocol?
Tell us which protocols and versions you need. We also add protocols on request.
Lumina VIP
hello@lumeeslab.comHelpful to include
- The protocols and versions
- Product types: VIP, assertion IP, memory model, transactor
- Your schedule